riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.

Browse Source
This commit is contained in:
Henry Cook
2013-03-20 14:05:12 -07:00
parent 6d2541aced
commit 273bd34091
5 changed files with 40 additions and 98 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
rocket/src/main/scala/tile.scala
View File

@ -24,7 +24,9 @@ case class RocketConfiguration(lnConf: LogicalNetworkConfiguration, co: Coherenc
class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Component(resetSignal) with ClientCoherenceAgent
{
val memPorts = 2 + confIn.vec
val dcachePortID = 0
val dcachePortId = 0
val icachePortId = 1
val vicachePortId = 2
implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(memPorts), databits = confIn.xprlen)
implicit val lnConf = confIn.lnConf
implicit val conf = confIn.copy(dcache = dcConf)
@ -38,24 +40,24 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
val icache = new Frontend()(confIn.icache, lnConf)
val dcache = new HellaCache
val arbiter = new MemArbiter(memPorts)
arbiter.io.requestor(dcachePortID) <> dcache.io.mem
arbiter.io.requestor(1) <> icache.io.mem
val arbiter = new UncachedTileLinkIOArbiter(memPorts)
arbiter.io.in(dcachePortId) <> dcache.io.mem
arbiter.io.in(icachePortId) <> icache.io.mem
io.tilelink.acquire <> arbiter.io.mem.acquire
io.tilelink.acquire_data <> dcache.io.mem.acquire_data
arbiter.io.mem.grant <> io.tilelink.grant
io.tilelink.grant_ack <> arbiter.io.mem.grant_ack
io.tilelink.acquire <> arbiter.io.out.acquire
io.tilelink.acquire_data <> arbiter.io.out.acquire_data
arbiter.io.out.grant <> io.tilelink.grant
io.tilelink.grant_ack <> arbiter.io.out.grant_ack
dcache.io.mem.probe <> io.tilelink.probe
io.tilelink.release_data <> dcache.io.mem.release_data
io.tilelink.release.valid := dcache.io.mem.release.valid
dcache.io.mem.release.ready := io.tilelink.release.ready
io.tilelink.release.bits := dcache.io.mem.release.bits
io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UFix(dcachePortID, log2Up(memPorts))) // Mimic client id extension done by MemArbiter for Acquires from either cache)
io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UFix(dcachePortId, log2Up(memPorts))) // Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
if (conf.vec) {
val vicache = new Frontend()(ICacheConfig(128, 1, conf.co), lnConf) // 128 sets x 1 ways (8KB)
arbiter.io.requestor(2) <> vicache.io.mem
arbiter.io.in(vicachePortId) <> vicache.io.mem
core.io.vimem <> vicache.io.cpu
}