riscv/rocket-chip
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Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.

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This commit is contained in:
Henry Cook
2013-03-20 14:05:12 -07:00
parent 6d2541aced
commit 273bd34091
5 changed files with 40 additions and 98 deletions
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5
rocket/src/main/scala/icache.scala
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@ -54,7 +54,7 @@ class Frontend(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) ex
{
val io = new Bundle {
val cpu = new CPUFrontendIO()(c).flip
val mem = new UncachedRequestorIO
val mem = new UncachedTileLinkIO
}
val btb = new rocketDpathBTB(c.nbtb)
@ -134,7 +134,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
val datablock = Bits(width = c.databits)
})
val invalidate = Bool(INPUT)
val mem = new UncachedRequestorIO
val mem = new UncachedTileLinkIO
}
val s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(4) { UFix() }
@ -246,6 +246,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
io.resp.valid := s2_hit
io.mem.acquire.valid := (state === s_request) && finish_q.io.enq.ready
io.mem.acquire.bits.payload := c.co.getUncachedReadAcquire(s2_addr >> UFix(c.offbits), UFix(0))
io.mem.acquire_data.valid := Bool(false)
io.mem.grant_ack <> FIFOedLogicalNetworkIOWrapper(finish_q.io.deq)
io.mem.grant.ready := Bool(true)