clean up addrmap flatten function
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33f13d5c49
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@ -75,13 +75,13 @@ object AddrMap {
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}
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class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) extends MemRegion {
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def isEmpty = entries.isEmpty
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def length = entries.size
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def numSlaves = entries.map(_.region.numSlaves).foldLeft(0)(_ + _)
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private val slavePorts = HashMap[String, Int]()
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private val mapping = HashMap[String, MemRegion]()
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def isEmpty = entries.isEmpty
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def length = entries.size
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def numSlaves = slavePorts.size
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val (size: BigInt, entries: Seq[AddrMapEntry], attr: MemAttr) = {
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var ind = 0
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var base = start
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@ -119,11 +119,11 @@ class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) exten
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(base - start, rebasedEntries, MemAttr(prot, cacheable))
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}
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val flatten: Seq[(String, MemRange)] = {
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val arr = new Array[(String, MemRange)](slavePorts.size)
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for ((name, port) <- slavePorts)
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arr(port) = (name, mapping(name).asInstanceOf[MemRange])
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arr
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val flatten: Seq[AddrMapEntry] = {
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mapping.toSeq.map {
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case (name, range: MemRange) => Some(AddrMapEntry(name, range))
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case _ => None
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}.flatten.sortBy(_.region.start)
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}
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def toRange: MemRange = MemRange(start, size, attr)
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@ -134,20 +134,19 @@ class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) exten
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def isInRegion(name: String, addr: UInt): Bool = mapping(name).containsAddress(addr)
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def isCacheable(addr: UInt): Bool = {
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flatten.filter(_._2.attr.cacheable).map { case (_, region) =>
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region.containsAddress(addr)
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}.foldLeft(Bool(false))(_ || _)
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flatten.filter(_.region.attr.cacheable).map(
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_.region.containsAddress(addr)
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).foldLeft(Bool(false))(_ || _)
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}
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def isValid(addr: UInt): Bool = {
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flatten.map { case (_, region) =>
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region.containsAddress(addr)
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}.foldLeft(Bool(false))(_ || _)
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flatten.map(_.region.containsAddress(addr)).foldLeft(Bool(false))(_ || _)
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}
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def getProt(addr: UInt): AddrMapProt = {
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val protForRegion = flatten.map { case (_, region) =>
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Mux(region.containsAddress(addr), UInt(region.attr.prot, AddrMapProt.SZ), UInt(0))
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val protForRegion = flatten.map { entry =>
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Mux(entry.region.containsAddress(addr),
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UInt(entry.region.attr.prot, AddrMapProt.SZ), UInt(0))
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}
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new AddrMapProt().fromBits(protForRegion.reduce(_|_))
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}
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@ -64,7 +64,12 @@ class TLB(implicit val p: Parameters) extends Module with HasTLBParameters {
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val mpu_ppn = Mux(do_refill, refill_ppn, passthrough_ppn)
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val prot = addrMap.getProt(mpu_ppn << pgIdxBits)
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val cacheable = addrMap.isCacheable(mpu_ppn << pgIdxBits)
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require(addrMap.flatten.forall { case (n, r) => (r.start | r.size) % (1 << pgIdxBits) == 0 })
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def pgaligned(r: MemRegion) = {
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val pgsize = 1 << pgIdxBits
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(r.start % pgsize) == 0 && (r.size % pgsize) == 0
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}
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require(addrMap.flatten.forall(e => pgaligned(e.region)),
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"MemoryMap regions must be page-aligned")
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val lookup_tag = Cat(io.ptw.ptbr.asid, io.req.bits.vpn(vpnBits-1,0))
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val vm_enabled = Bool(usingVM) && io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough
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@ -312,7 +312,7 @@ class BaseConfig extends Config (
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TileLinkParameters(
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coherencePolicy = new MICoherence(
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new NullRepresentation(site(NBanksPerMemoryChannel))),
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nManagers = globalAddrMap.subMap("io").flatten.size,
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nManagers = globalAddrMap.subMap("io").numSlaves,
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nCachingClients = 0,
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nCachelessClients = 1,
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maxClientXacts = 4,
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@ -192,8 +192,11 @@ class OuterMemorySystem(implicit p: Parameters) extends AbstractOuterMemorySyste
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// TODO: the code to print this stuff should live somewhere else
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println("Generated Address Map")
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for ((name, region) <- p(GlobalAddrMap).flatten) {
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println(f"\t$name%s ${region.start}%x - ${region.start + region.size - 1}%x")
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for (entry <- p(GlobalAddrMap).flatten) {
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val name = entry.name
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val start = entry.region.start
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val end = entry.region.start + entry.region.size - 1
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println(f"\t$name%s $start%x - $end%x")
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}
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println("Generated Configuration String")
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println(new String(p(ConfigString)))
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