diff --git a/junctions/src/main/scala/addrmap.scala b/junctions/src/main/scala/addrmap.scala
index 0424509c..da477316 100644
--- a/junctions/src/main/scala/addrmap.scala
+++ b/junctions/src/main/scala/addrmap.scala
@@ -75,13 +75,13 @@ object AddrMap {
 }
 
 class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) extends MemRegion {
-  def isEmpty = entries.isEmpty
-  def length = entries.size
-  def numSlaves = entries.map(_.region.numSlaves).foldLeft(0)(_ + _)
-
   private val slavePorts = HashMap[String, Int]()
   private val mapping = HashMap[String, MemRegion]()
 
+  def isEmpty = entries.isEmpty
+  def length = entries.size
+  def numSlaves = slavePorts.size
+
   val (size: BigInt, entries: Seq[AddrMapEntry], attr: MemAttr) = {
     var ind = 0
     var base = start
@@ -119,11 +119,11 @@ class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) exten
     (base - start, rebasedEntries, MemAttr(prot, cacheable))
   }
 
-  val flatten: Seq[(String, MemRange)] = {
-    val arr = new Array[(String, MemRange)](slavePorts.size)
-    for ((name, port) <- slavePorts)
-      arr(port) = (name, mapping(name).asInstanceOf[MemRange])
-    arr
+  val flatten: Seq[AddrMapEntry] = {
+    mapping.toSeq.map {
+      case (name, range: MemRange) => Some(AddrMapEntry(name, range))
+      case _ => None
+    }.flatten.sortBy(_.region.start)
   }
 
   def toRange: MemRange = MemRange(start, size, attr)
@@ -134,20 +134,19 @@ class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) exten
   def isInRegion(name: String, addr: UInt): Bool = mapping(name).containsAddress(addr)
 
   def isCacheable(addr: UInt): Bool = {
-    flatten.filter(_._2.attr.cacheable).map { case (_, region) =>
-      region.containsAddress(addr)
-    }.foldLeft(Bool(false))(_ || _)
+    flatten.filter(_.region.attr.cacheable).map(
+      _.region.containsAddress(addr)
+    ).foldLeft(Bool(false))(_ || _)
   }
 
   def isValid(addr: UInt): Bool = {
-    flatten.map { case (_, region) =>
-      region.containsAddress(addr)
-    }.foldLeft(Bool(false))(_ || _)
+    flatten.map(_.region.containsAddress(addr)).foldLeft(Bool(false))(_ || _)
   }
 
   def getProt(addr: UInt): AddrMapProt = {
-    val protForRegion = flatten.map { case (_, region) =>
-      Mux(region.containsAddress(addr), UInt(region.attr.prot, AddrMapProt.SZ), UInt(0))
+    val protForRegion = flatten.map { entry =>
+      Mux(entry.region.containsAddress(addr),
+        UInt(entry.region.attr.prot, AddrMapProt.SZ), UInt(0))
     }
     new AddrMapProt().fromBits(protForRegion.reduce(_|_))
   }
diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index 1437715b..e412a34a 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -64,7 +64,12 @@ class TLB(implicit val p: Parameters) extends Module with HasTLBParameters {
   val mpu_ppn = Mux(do_refill, refill_ppn, passthrough_ppn)
   val prot = addrMap.getProt(mpu_ppn << pgIdxBits)
   val cacheable = addrMap.isCacheable(mpu_ppn << pgIdxBits)
-  require(addrMap.flatten.forall { case (n, r) => (r.start | r.size) % (1 << pgIdxBits) == 0 })
+  def pgaligned(r: MemRegion) = {
+    val pgsize = 1 << pgIdxBits
+    (r.start % pgsize) == 0 && (r.size % pgsize) == 0
+  }
+  require(addrMap.flatten.forall(e => pgaligned(e.region)),
+    "MemoryMap regions must be page-aligned")
   
   val lookup_tag = Cat(io.ptw.ptbr.asid, io.req.bits.vpn(vpnBits-1,0))
   val vm_enabled = Bool(usingVM) && io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index f4832b8b..6e3ea029 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -312,7 +312,7 @@ class BaseConfig extends Config (
         TileLinkParameters(
           coherencePolicy = new MICoherence(
             new NullRepresentation(site(NBanksPerMemoryChannel))),
-          nManagers = globalAddrMap.subMap("io").flatten.size,
+          nManagers = globalAddrMap.subMap("io").numSlaves,
           nCachingClients = 0,
           nCachelessClients = 1,
           maxClientXacts = 4,
diff --git a/src/main/scala/Coreplex.scala b/src/main/scala/Coreplex.scala
index 41df986c..806f959d 100644
--- a/src/main/scala/Coreplex.scala
+++ b/src/main/scala/Coreplex.scala
@@ -192,8 +192,11 @@ class OuterMemorySystem(implicit p: Parameters) extends AbstractOuterMemorySyste
 
   // TODO: the code to print this stuff should live somewhere else
   println("Generated Address Map")
-  for ((name, region) <- p(GlobalAddrMap).flatten) {
-    println(f"\t$name%s ${region.start}%x - ${region.start + region.size - 1}%x")
+  for (entry <- p(GlobalAddrMap).flatten) {
+    val name = entry.name
+    val start = entry.region.start
+    val end = entry.region.start + entry.region.size - 1
+    println(f"\t$name%s $start%x - $end%x")
   }
   println("Generated Configuration String")
   println(new String(p(ConfigString)))