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clean up addrmap flatten function

This commit is contained in:
Howard Mao 2016-08-09 22:14:32 -07:00
parent 33f13d5c49
commit 2645f74af2
4 changed files with 28 additions and 21 deletions

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@ -75,13 +75,13 @@ object AddrMap {
} }
class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) extends MemRegion { class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) extends MemRegion {
def isEmpty = entries.isEmpty
def length = entries.size
def numSlaves = entries.map(_.region.numSlaves).foldLeft(0)(_ + _)
private val slavePorts = HashMap[String, Int]() private val slavePorts = HashMap[String, Int]()
private val mapping = HashMap[String, MemRegion]() private val mapping = HashMap[String, MemRegion]()
def isEmpty = entries.isEmpty
def length = entries.size
def numSlaves = slavePorts.size
val (size: BigInt, entries: Seq[AddrMapEntry], attr: MemAttr) = { val (size: BigInt, entries: Seq[AddrMapEntry], attr: MemAttr) = {
var ind = 0 var ind = 0
var base = start var base = start
@ -119,11 +119,11 @@ class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) exten
(base - start, rebasedEntries, MemAttr(prot, cacheable)) (base - start, rebasedEntries, MemAttr(prot, cacheable))
} }
val flatten: Seq[(String, MemRange)] = { val flatten: Seq[AddrMapEntry] = {
val arr = new Array[(String, MemRange)](slavePorts.size) mapping.toSeq.map {
for ((name, port) <- slavePorts) case (name, range: MemRange) => Some(AddrMapEntry(name, range))
arr(port) = (name, mapping(name).asInstanceOf[MemRange]) case _ => None
arr }.flatten.sortBy(_.region.start)
} }
def toRange: MemRange = MemRange(start, size, attr) def toRange: MemRange = MemRange(start, size, attr)
@ -134,20 +134,19 @@ class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) exten
def isInRegion(name: String, addr: UInt): Bool = mapping(name).containsAddress(addr) def isInRegion(name: String, addr: UInt): Bool = mapping(name).containsAddress(addr)
def isCacheable(addr: UInt): Bool = { def isCacheable(addr: UInt): Bool = {
flatten.filter(_._2.attr.cacheable).map { case (_, region) => flatten.filter(_.region.attr.cacheable).map(
region.containsAddress(addr) _.region.containsAddress(addr)
}.foldLeft(Bool(false))(_ || _) ).foldLeft(Bool(false))(_ || _)
} }
def isValid(addr: UInt): Bool = { def isValid(addr: UInt): Bool = {
flatten.map { case (_, region) => flatten.map(_.region.containsAddress(addr)).foldLeft(Bool(false))(_ || _)
region.containsAddress(addr)
}.foldLeft(Bool(false))(_ || _)
} }
def getProt(addr: UInt): AddrMapProt = { def getProt(addr: UInt): AddrMapProt = {
val protForRegion = flatten.map { case (_, region) => val protForRegion = flatten.map { entry =>
Mux(region.containsAddress(addr), UInt(region.attr.prot, AddrMapProt.SZ), UInt(0)) Mux(entry.region.containsAddress(addr),
UInt(entry.region.attr.prot, AddrMapProt.SZ), UInt(0))
} }
new AddrMapProt().fromBits(protForRegion.reduce(_|_)) new AddrMapProt().fromBits(protForRegion.reduce(_|_))
} }

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@ -64,7 +64,12 @@ class TLB(implicit val p: Parameters) extends Module with HasTLBParameters {
val mpu_ppn = Mux(do_refill, refill_ppn, passthrough_ppn) val mpu_ppn = Mux(do_refill, refill_ppn, passthrough_ppn)
val prot = addrMap.getProt(mpu_ppn << pgIdxBits) val prot = addrMap.getProt(mpu_ppn << pgIdxBits)
val cacheable = addrMap.isCacheable(mpu_ppn << pgIdxBits) val cacheable = addrMap.isCacheable(mpu_ppn << pgIdxBits)
require(addrMap.flatten.forall { case (n, r) => (r.start | r.size) % (1 << pgIdxBits) == 0 }) def pgaligned(r: MemRegion) = {
val pgsize = 1 << pgIdxBits
(r.start % pgsize) == 0 && (r.size % pgsize) == 0
}
require(addrMap.flatten.forall(e => pgaligned(e.region)),
"MemoryMap regions must be page-aligned")
val lookup_tag = Cat(io.ptw.ptbr.asid, io.req.bits.vpn(vpnBits-1,0)) val lookup_tag = Cat(io.ptw.ptbr.asid, io.req.bits.vpn(vpnBits-1,0))
val vm_enabled = Bool(usingVM) && io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough val vm_enabled = Bool(usingVM) && io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough

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@ -312,7 +312,7 @@ class BaseConfig extends Config (
TileLinkParameters( TileLinkParameters(
coherencePolicy = new MICoherence( coherencePolicy = new MICoherence(
new NullRepresentation(site(NBanksPerMemoryChannel))), new NullRepresentation(site(NBanksPerMemoryChannel))),
nManagers = globalAddrMap.subMap("io").flatten.size, nManagers = globalAddrMap.subMap("io").numSlaves,
nCachingClients = 0, nCachingClients = 0,
nCachelessClients = 1, nCachelessClients = 1,
maxClientXacts = 4, maxClientXacts = 4,

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@ -192,8 +192,11 @@ class OuterMemorySystem(implicit p: Parameters) extends AbstractOuterMemorySyste
// TODO: the code to print this stuff should live somewhere else // TODO: the code to print this stuff should live somewhere else
println("Generated Address Map") println("Generated Address Map")
for ((name, region) <- p(GlobalAddrMap).flatten) { for (entry <- p(GlobalAddrMap).flatten) {
println(f"\t$name%s ${region.start}%x - ${region.start + region.size - 1}%x") val name = entry.name
val start = entry.region.start
val end = entry.region.start + entry.region.size - 1
println(f"\t$name%s $start%x - $end%x")
} }
println("Generated Configuration String") println("Generated Configuration String")
println(new String(p(ConfigString))) println(new String(p(ConfigString)))