riscv/rocket-chip
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clean up addrmap flatten function

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This commit is contained in:
Howard Mao
2016-08-09 22:14:32 -07:00
parent 33f13d5c49
commit 2645f74af2
4 changed files with 28 additions and 21 deletions
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7
rocket/src/main/scala/tlb.scala
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@ -64,7 +64,12 @@ class TLB(implicit val p: Parameters) extends Module with HasTLBParameters {
val mpu_ppn = Mux(do_refill, refill_ppn, passthrough_ppn)
val prot = addrMap.getProt(mpu_ppn << pgIdxBits)
val cacheable = addrMap.isCacheable(mpu_ppn << pgIdxBits)
require(addrMap.flatten.forall { case (n, r) => (r.start | r.size) % (1 << pgIdxBits) == 0 })
def pgaligned(r: MemRegion) = {
val pgsize = 1 << pgIdxBits
(r.start % pgsize) == 0 && (r.size % pgsize) == 0
}
require(addrMap.flatten.forall(e => pgaligned(e.region)),
"MemoryMap regions must be page-aligned")
val lookup_tag = Cat(io.ptw.ptbr.asid, io.req.bits.vpn(vpnBits-1,0))
val vm_enabled = Bool(usingVM) && io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough