sync up rocket with new isa
This commit is contained in:
Andrew Waterman
@ -22,10 +22,11 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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// execute definitions
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val ex_reg_pc = Reg(UInt())
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val ex_reg_inst = Reg(Bits())
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val ex_reg_waddr = Reg(UInt())
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val ex_reg_ctrl_fn_dw = Reg(UInt())
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val ex_reg_ctrl_fn_alu = Reg(UInt())
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val ex_reg_sel_alu2 = Reg(UInt())
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val ex_reg_sel_alu1 = Reg(UInt())
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val ex_reg_sel_imm = Reg(UInt())
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val ex_reg_ctrl_sel_wb = Reg(UInt())
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val ex_reg_kill = Reg(Bool())
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val ex_reg_rs1_bypass = Reg(Bool())
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@ -38,7 +39,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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// memory definitions
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val mem_reg_pc = Reg(UInt())
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val mem_reg_inst = Reg(Bits())
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val mem_reg_waddr = Reg(UInt())
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val mem_reg_wdata = Reg(Bits())
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val mem_reg_kill = Reg(Bool())
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val mem_reg_store_data = Reg(Bits())
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@ -70,30 +70,33 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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// bypass muxes
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val id_rs1_zero = id_raddr1 === UInt(0)
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val id_rs1_ex_bypass = io.ctrl.ex_wen && id_raddr1 === ex_reg_waddr
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val id_rs1_mem_bypass = io.ctrl.mem_wen && id_raddr1 === mem_reg_waddr
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val id_rs1_ex_bypass = io.ctrl.ex_wen && id_raddr1 === io.ctrl.ex_waddr
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val id_rs1_mem_bypass = io.ctrl.mem_wen && id_raddr1 === io.ctrl.mem_waddr
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val id_rs1_bypass = id_rs1_zero || id_rs1_ex_bypass || id_rs1_mem_bypass || io.ctrl.mem_ll_bypass_rs1
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val id_rs1_bypass_src = Mux(id_rs1_zero, UInt(0), Mux(id_rs1_ex_bypass, UInt(1), Mux(io.ctrl.mem_load, UInt(3), UInt(2))))
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val id_rs1 = Mux(wb_wen && id_raddr1 === wb_reg_waddr, wb_wdata, readRF(id_raddr1))
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val id_rs2_zero = id_raddr2 === UInt(0)
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val id_rs2_ex_bypass = io.ctrl.ex_wen && id_raddr2 === ex_reg_waddr
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val id_rs2_mem_bypass = io.ctrl.mem_wen && id_raddr2 === mem_reg_waddr
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val id_rs2_ex_bypass = io.ctrl.ex_wen && id_raddr2 === io.ctrl.ex_waddr
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val id_rs2_mem_bypass = io.ctrl.mem_wen && id_raddr2 === io.ctrl.mem_waddr
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val id_rs2_bypass = id_rs2_zero || id_rs2_ex_bypass || id_rs2_mem_bypass || io.ctrl.mem_ll_bypass_rs2
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val id_rs2_bypass_src = Mux(id_rs2_zero, UInt(0), Mux(id_rs2_ex_bypass, UInt(1), Mux(io.ctrl.mem_load, UInt(3), UInt(2))))
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val id_rs2 = Mux(wb_wen && id_raddr2 === wb_reg_waddr, wb_wdata, readRF(id_raddr2))
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// immediate generation
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def imm(sel: Bits, inst: Bits) = {
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val lsbs = Mux(sel === A2_LTYPE || sel === A2_ZERO, Bits(0),
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Mux(sel === A2_BTYPE, Cat(inst(31,27), inst(16,10)),
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Mux(sel === A2_JTYPE, inst(18,7),
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inst(21,10))))
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val msbs = Mux(sel === A2_ZERO, SInt(0),
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Mux(sel === A2_LTYPE, inst(26,7).toSInt,
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Mux(sel === A2_JTYPE, inst(31,19).toSInt,
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Mux(sel === A2_ITYPE, inst(21), inst(31)).toSInt)))
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Cat(msbs, lsbs).toSInt
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val sign = inst(10).toSInt
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val b30_20 = Mux(sel === IMM_U, inst(21,11).toSInt, sign)
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val b19_12 = Mux(sel != IMM_U && sel != IMM_UJ, sign,
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Cat(inst(9,7), inst(26,22)).toSInt)
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val b11 = Mux(sel === IMM_U, SInt(0),
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Mux(sel === IMM_SB || sel === IMM_UJ, inst(11).toSInt, sign))
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val b10_6 = Mux(sel === IMM_S || sel === IMM_SB, inst(31,27),
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Mux(sel === IMM_U, Bits(0), inst(21,17)))
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val b5_1 = Mux(sel === IMM_U, Bits(0), inst(16,12))
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val b0 = Mux(sel === IMM_I || sel === IMM_S, inst(11), Bits(0))
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Cat(sign, b30_20, b19_12, b11, b10_6, b5_1, b0).toSInt
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}
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io.ctrl.inst := id_inst
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@ -104,13 +107,15 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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when (!io.ctrl.killd) {
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ex_reg_pc := id_pc
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ex_reg_inst := id_inst
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ex_reg_waddr := Mux(io.ctrl.sel_wa === WA_RD, id_inst(31,27).toUInt, RA)
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ex_reg_ctrl_fn_dw := io.ctrl.fn_dw.toUInt
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ex_reg_ctrl_fn_alu := io.ctrl.fn_alu
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ex_reg_sel_alu2 := io.ctrl.sel_alu2
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ex_reg_sel_alu1 := io.ctrl.sel_alu1
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ex_reg_sel_imm := io.ctrl.sel_imm
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ex_reg_ctrl_sel_wb := io.ctrl.sel_wb
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ex_reg_rs1_bypass := id_rs1_bypass && io.ctrl.ren1
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ex_reg_rs2_bypass := id_rs2_bypass && io.ctrl.ren2
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when (io.ctrl.ren1) {
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ex_reg_rs1_bypass := id_rs1_bypass
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ex_reg_rs1_lsb := id_rs1_bypass_src
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when (!id_rs1_bypass) {
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ex_reg_rs1_lsb := id_rs1(id_rs1_bypass_src.getWidth-1,0)
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@ -118,7 +123,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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}
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}
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when (io.ctrl.ren2) {
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ex_reg_rs2_bypass := id_rs2_bypass
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ex_reg_rs2_lsb := id_rs2_bypass_src
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when (!id_rs2_bypass) {
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ex_reg_rs2_lsb := id_rs2(id_rs2_bypass_src.getWidth-1,0)
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@ -136,21 +140,27 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UInt(2), wb_reg_wdata,
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Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UInt(1), mem_reg_wdata,
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Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UInt(0), Bits(0),
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Cat(ex_reg_rs1_msb, ex_reg_rs1_lsb)))))
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Mux(ex_reg_sel_alu1 === A1_ZERO, Bits(0),
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Cat(ex_reg_rs1_msb, ex_reg_rs1_lsb))))))
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val ex_rs2 =
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Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UInt(3) && Bool(conf.fastLoadWord), dmem_resp_data,
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Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UInt(2), wb_reg_wdata,
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Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UInt(1), mem_reg_wdata,
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Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UInt(0), Bits(0),
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Cat(ex_reg_rs2_msb, ex_reg_rs2_lsb)))))
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val ex_imm = imm(ex_reg_sel_alu2, ex_reg_inst)
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val ex_op2 = Mux(ex_reg_sel_alu2 != A2_RTYPE, ex_imm, ex_rs2)
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val ex_imm = imm(ex_reg_sel_imm, ex_reg_inst)
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val ex_op1 = Mux(ex_reg_sel_alu1 === A1_PC, ex_reg_pc.toSInt, ex_rs1)
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val ex_op2 = Mux(ex_reg_sel_alu2 === A2_RS2, ex_rs2.toSInt,
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Mux(ex_reg_sel_alu2 === A2_IMM, ex_imm,
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Mux(ex_reg_sel_alu2 === A2_ZERO, SInt(0),
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SInt(4))))
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val alu = Module(new ALU)
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alu.io.dw := ex_reg_ctrl_fn_dw;
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alu.io.fn := ex_reg_ctrl_fn_alu;
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alu.io.in2 := ex_op2.toUInt
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alu.io.in1 := ex_rs1.toUInt
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alu.io.in1 := ex_op1.toUInt
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// multiplier and divider
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val div = Module(new MulDiv(mulUnroll = if (conf.fastMulDiv) 8 else 1,
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@ -160,13 +170,13 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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div.io.req.bits.fn := ex_reg_ctrl_fn_alu
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div.io.req.bits.in1 := ex_rs1
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div.io.req.bits.in2 := ex_rs2
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div.io.req.bits.tag := ex_reg_waddr
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div.io.req.bits.tag := io.ctrl.ex_waddr
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div.io.kill := io.ctrl.div_mul_kill
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div.io.resp.ready := !io.ctrl.mem_wen
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io.ctrl.div_mul_rdy := div.io.req.ready
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io.fpu.fromint_data := ex_rs1
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io.ctrl.ex_waddr := ex_reg_waddr
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io.ctrl.ex_waddr := ex_reg_inst(31,27)
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def vaSign(a0: UInt, ea: Bits) = {
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// efficient means to compress 64-bit VA into VADDR_BITS+1 bits
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@ -177,13 +187,17 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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Mux(a === SInt(-1) || a === SInt(-2), e === SInt(-1),
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e(0)))
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}
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val ex_effective_address = Cat(vaSign(ex_rs1, alu.io.adder_out), alu.io.adder_out(VADDR_BITS-1,0)).toUInt
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val ex_br_base = Mux(io.ctrl.ex_jalr, ex_rs1, ex_reg_pc)
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val ex_br_offset = Mux(io.ctrl.ex_predicted_taken && !io.ctrl.ex_jalr, SInt(4), ex_imm)
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val ex_br64 = ex_br_base + ex_br_offset
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val ex_br_msb = Mux(io.ctrl.ex_jalr, vaSign(ex_rs1, ex_br64), vaSign(ex_reg_pc, ex_br64))
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val ex_br_addr = Cat(ex_br_msb, ex_br64(VADDR_BITS-1,0))
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// D$ request interface (registered inside D$ module)
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// other signals (req_val, req_rdy) connect to control module
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io.dmem.req.bits.addr := ex_effective_address
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io.dmem.req.bits.addr := Cat(vaSign(ex_rs1, alu.io.adder_out), alu.io.adder_out(VADDR_BITS-1,0)).toUInt
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io.dmem.req.bits.data := Mux(io.ctrl.mem_fp_val, io.fpu.store_data, mem_reg_store_data)
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io.dmem.req.bits.tag := Cat(ex_reg_waddr, io.ctrl.ex_fp_val)
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io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_fp_val)
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require(io.dmem.req.bits.tag.getWidth >= 6)
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// processor control regfile read
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@ -209,26 +223,20 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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Mux(io.ctrl.ex_br_type === BR_GEU, ex_rs1 >= ex_rs2,
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io.ctrl.ex_br_type === BR_J))))))
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val ex_pc_plus4 = ex_reg_pc.toSInt + Mux(ex_reg_sel_alu2 === A2_LTYPE, ex_reg_inst(26,7).toSInt << 12, SInt(4))
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val ex_branch_target = ex_reg_pc.toSInt + (ex_imm << 1)
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val ex_jalr_target = (ex_effective_address >> 1 << 1).toSInt
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val tsc_reg = WideCounter(64)
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val irt_reg = WideCounter(64, io.ctrl.wb_valid)
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// writeback select mux
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val ex_wdata =
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Mux(ex_reg_ctrl_sel_wb === WB_PC, ex_pc_plus4,
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Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg.value,
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Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg.value,
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alu.io.out))).toBits // WB_ALU
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alu.io.out)).toBits // WB_ALU
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// memory stage
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mem_reg_kill := ex_reg_kill
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when (!ex_reg_kill) {
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mem_reg_pc := ex_reg_pc
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mem_reg_inst := ex_reg_inst
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mem_reg_waddr := ex_reg_waddr
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mem_reg_wdata := ex_wdata
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mem_reg_rs1 := ex_rs1
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mem_reg_rs2 := ex_rs2
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@ -238,7 +246,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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}
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// for load/use hazard detection (load byte/halfword)
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io.ctrl.mem_waddr := mem_reg_waddr;
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io.ctrl.mem_waddr := mem_reg_inst(31,27)
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// writeback arbitration
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val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).toBool
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@ -266,8 +274,8 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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// writeback stage
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when (!mem_reg_kill) {
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wb_reg_pc := mem_reg_pc
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wb_reg_waddr := io.ctrl.mem_waddr
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wb_reg_inst := mem_reg_inst
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wb_reg_waddr := mem_reg_waddr
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wb_reg_wdata := Mux(io.ctrl.mem_fp_val && io.ctrl.mem_wen, io.fpu.toint_data, mem_reg_wdata)
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wb_reg_rs1 := mem_reg_rs1
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wb_reg_rs2 := mem_reg_rs2
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@ -322,10 +330,9 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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// hook up I$
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io.imem.req.bits.currentpc := ex_reg_pc
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io.imem.req.bits.pc :=
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Mux(io.ctrl.sel_pc === PC_EX4, ex_pc_plus4,
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Mux(io.ctrl.sel_pc === PC_EX, Mux(io.ctrl.ex_jalr, ex_jalr_target, ex_branch_target),
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Mux(io.ctrl.sel_pc === PC_EX, ex_br_addr,
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Mux(io.ctrl.sel_pc === PC_PCR, pcr.io.evec,
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wb_reg_pc))).toUInt // PC_WB
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wb_reg_pc)).toUInt // PC_WB
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printf("C: %d [%d] pc=[%x] W[r%d=%x] R[r%d=%x] R[r%d=%x] inst=[%x] %s\n",
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tsc_reg(32,0), io.ctrl.wb_valid, wb_reg_pc,
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