diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala
index 3176608e..702fe5db 100644
--- a/rocket/src/main/scala/htif.scala
+++ b/rocket/src/main/scala/htif.scala
@@ -80,8 +80,13 @@ class rocketHTIF(w: Int, ncores: Int) extends Component
 
   val mem_acked = Reg(resetVal = Bool(false))
   val mem_gxid = Reg() { Bits() }
+  val mem_needs_ack = Reg() { Bool() }
   val mem_nacked = Reg(resetVal = Bool(false))
-  when (io.mem.xact_rep.valid) { mem_acked := Bool(true); mem_gxid := io.mem.xact_rep.bits.global_xact_id }
+  when (io.mem.xact_rep.valid) { 
+    mem_acked := Bool(true)
+    mem_gxid := io.mem.xact_rep.bits.global_xact_id
+    mem_needs_ack := io.mem.xact_rep.bits.require_ack  
+  }
   when (io.mem.xact_abort.valid) { mem_nacked := Bool(true) }
 
   val state_rx :: state_pcr :: state_mem_req :: state_mem_wdata :: state_mem_wresp :: state_mem_rdata :: state_mem_finish :: state_tx :: Nil = Enum(8) { UFix() }
@@ -152,7 +157,7 @@ class rocketHTIF(w: Int, ncores: Int) extends Component
   io.mem.xact_init.bits.address := addr >> UFix(OFFSET_BITS-3)
   io.mem.xact_init_data.valid:= state === state_mem_wdata
   io.mem.xact_init_data.bits.data := mem_req_data
-  io.mem.xact_finish.valid := state === state_mem_finish
+  io.mem.xact_finish.valid := (state === state_mem_finish) && mem_needs_ack
   io.mem.xact_finish.bits.global_xact_id := mem_gxid
 
   pcr_done := Bool(false)
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 4e9aa368..b1178f97 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -127,7 +127,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
   tag_hit := any_hit
 
   val finish_q = (new queue(1)) { new TransactionFinish }
-  finish_q.io.enq.valid := refill_done
+  finish_q.io.enq.valid := refill_done && io.mem.xact_rep.bits.require_ack
   finish_q.io.enq.bits.global_xact_id := io.mem.xact_rep.bits.global_xact_id
 
   // output signals
diff --git a/rocket/src/main/scala/icache_prefetch.scala b/rocket/src/main/scala/icache_prefetch.scala
index 9c2d47e5..425f95d6 100644
--- a/rocket/src/main/scala/icache_prefetch.scala
+++ b/rocket/src/main/scala/icache_prefetch.scala
@@ -46,7 +46,7 @@ class rocketIPrefetcher extends Component() {
   when (ip_mem_resp_val) { fill_cnt := fill_cnt + UFix(1) }
   val fill_done = fill_cnt.andR && ip_mem_resp_val
 
-  finish_q.io.enq.valid := fill_done
+  finish_q.io.enq.valid := fill_done && io.mem.xact_rep.bits.require_ack
   finish_q.io.enq.bits.global_xact_id := io.mem.xact_rep.bits.global_xact_id
   
   val forward = Reg(resetVal = Bool(false))
@@ -59,6 +59,7 @@ class rocketIPrefetcher extends Component() {
                                 forward && ip_mem_resp_abort
   io.icache.xact_rep.valid  := io.mem.xact_rep.valid && !io.mem.xact_rep.bits.tile_xact_id(0) || (forward && pdq.io.deq.valid)
   io.icache.xact_rep.bits.data := Mux(forward, pdq.io.deq.bits, io.mem.xact_rep.bits.data)
+  io.icache.xact_rep.bits.require_ack := !forward && io.mem.xact_rep.bits.require_ack
   
   pdq.io.flush := Reg(demand_miss && !hit || (state === s_bad_resp_wait), resetVal = Bool(false))
   pdq.io.enq.bits := io.mem.xact_rep.bits.data