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Let isRead be true for store-conditional

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This works around a deadlock bug in the L1 D$, and is arguably true.
This commit is contained in:
Andrew Waterman 2015-09-25 15:27:20 -07:00
parent 308022210a
commit 2179cb64ae
1 changed files with 1 additions and 1 deletions
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uncore/src/main/scala/consts.scala
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@ -43,7 +43,7 @@ trait MemoryOpConstants {
def isAMO(cmd: UInt) = cmd(3) || cmd === M_XA_SWAP def isAMO(cmd: UInt) = cmd(3) || cmd === M_XA_SWAP
def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
def isRead(cmd: UInt) = cmd === M_XRD || cmd === M_XLR || isAMO(cmd) def isRead(cmd: UInt) = cmd === M_XRD || cmd === M_XLR || cmd === M_XSC || isAMO(cmd)
def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_XSC || isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_XSC || isAMO(cmd)
def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
} }