riscv/rocket-chip
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test_mode_reset: fix typos

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This commit is contained in:
Megan Wachs 2017-09-17 13:51:40 -07:00
parent 641a8e7eab
commit 215e072e5c
1 changed files with 6 additions and 4 deletions
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10
src/main/scala/devices/debug/Periphery.scala
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@ -38,7 +38,12 @@ trait HasPeripheryDebugBundle {
val debug: DebugIO
def connectDebug(c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2, psd: PSDTestMode) {
def connectDebug(c: Clock,
r: Bool,
out: Bool,
tckHalfPeriod: Int = 2,
cmdDelay: Int = 2,
psd: PSDTestMode = new PSDTestMode().fromBits(0.U)): Unit = {
debug.clockeddmi.foreach { d =>
val dtm = Module(new SimDTM).connect(c, r, d, out)
}
@ -49,9 +54,6 @@ trait HasPeripheryDebugBundle {
debug.psd.foreach { _ <> psd }
}
def connectDebug(c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2) =
connectDebug(c, r, out, tckHalfPeriod, cmdDelay, new PSDTestMode.fromBits(0.U))
}
trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryDebugBundle {
val outer: HasPeripheryDebug