From 215e072e5c4ffd5ec5582464555336e13943cb6c Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Sun, 17 Sep 2017 13:51:40 -0700 Subject: [PATCH] test_mode_reset: fix typos --- src/main/scala/devices/debug/Periphery.scala | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala index d1e05653..ecd612d9 100644 --- a/src/main/scala/devices/debug/Periphery.scala +++ b/src/main/scala/devices/debug/Periphery.scala @@ -38,7 +38,12 @@ trait HasPeripheryDebugBundle { val debug: DebugIO - def connectDebug(c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2, psd: PSDTestMode) { + def connectDebug(c: Clock, + r: Bool, + out: Bool, + tckHalfPeriod: Int = 2, + cmdDelay: Int = 2, + psd: PSDTestMode = new PSDTestMode().fromBits(0.U)): Unit = { debug.clockeddmi.foreach { d => val dtm = Module(new SimDTM).connect(c, r, d, out) } @@ -49,9 +54,6 @@ trait HasPeripheryDebugBundle { debug.psd.foreach { _ <> psd } } - def connectDebug(c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2) = - connectDebug(c, r, out, tckHalfPeriod, cmdDelay, new PSDTestMode.fromBits(0.U)) - } trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryDebugBundle { val outer: HasPeripheryDebug