riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Made xact_rep an ioValid, removed has_data member

Browse Source
This commit is contained in:
Henry Cook 2012-03-01 17:03:56 -08:00
parent 4e33b68bea
commit 2152b0283d
1 changed files with 6 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
uncore/coherence.scala
View File

@ -14,10 +14,9 @@ class MemReqCmd() extends Bundle
val tag = Bits(width = MEM_TAG_BITS)
}
class MemResp () extends Bundle
class MemResp () extends MemData
{
val tag = Bits(width = MEM_TAG_BITS)
val data = Bits(width = MEM_DATA_BITS)
}
class ioMem() extends Bundle
@ -72,7 +71,6 @@ class ProbeReplyData extends MemData
class TransactionReply extends MemData {
val t_type = Bits(width = TTYPE_BITS)
val has_data = Bool()
val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
}
@ -88,7 +86,7 @@ class ioTileLink extends Bundle {
val probe_req = (new ioDecoupled) { new ProbeRequest() }
val probe_rep = (new ioDecoupled) { new ProbeReply() }.flip
val probe_rep_data = (new ioDecoupled) { new ProbeReplyData() }.flip
val xact_rep = (new ioDecoupled) { new TransactionReply() }
val xact_rep = (new ioValid) { new TransactionReply() }
val xact_finish = (new ioDecoupled) { new TransactionFinish() }.flip
}
@ -173,6 +171,10 @@ trait FourStateCoherence extends CoherencePolicy {
}
state.toBits
}
def replyTypeHasData (reply: TransactionReply): Bool = {
(reply.t_type != X_WRITE_UNCACHED)
}
}
class XactTracker(id: Int) extends Component with CoherencePolicy {