From 2152b0283d0a3438b644210166d2122ba64c2580 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 1 Mar 2012 17:03:56 -0800 Subject: [PATCH] Made xact_rep an ioValid, removed has_data member --- uncore/coherence.scala | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/uncore/coherence.scala b/uncore/coherence.scala index 0ded6f22..12c1e4a9 100644 --- a/uncore/coherence.scala +++ b/uncore/coherence.scala @@ -14,10 +14,9 @@ class MemReqCmd() extends Bundle val tag = Bits(width = MEM_TAG_BITS) } -class MemResp () extends Bundle +class MemResp () extends MemData { val tag = Bits(width = MEM_TAG_BITS) - val data = Bits(width = MEM_DATA_BITS) } class ioMem() extends Bundle @@ -72,7 +71,6 @@ class ProbeReplyData extends MemData class TransactionReply extends MemData { val t_type = Bits(width = TTYPE_BITS) - val has_data = Bool() val tile_xact_id = Bits(width = TILE_XACT_ID_BITS) val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS) } @@ -88,7 +86,7 @@ class ioTileLink extends Bundle { val probe_req = (new ioDecoupled) { new ProbeRequest() } val probe_rep = (new ioDecoupled) { new ProbeReply() }.flip val probe_rep_data = (new ioDecoupled) { new ProbeReplyData() }.flip - val xact_rep = (new ioDecoupled) { new TransactionReply() } + val xact_rep = (new ioValid) { new TransactionReply() } val xact_finish = (new ioDecoupled) { new TransactionFinish() }.flip } @@ -173,6 +171,10 @@ trait FourStateCoherence extends CoherencePolicy { } state.toBits } + + def replyTypeHasData (reply: TransactionReply): Bool = { + (reply.t_type != X_WRITE_UNCACHED) + } } class XactTracker(id: Int) extends Component with CoherencePolicy {