riscv/rocket-chip
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Drive invalidate_lr signal

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The DCache input for invalidating LR reservations was dangling.  Now
we wire it to false.
This commit is contained in:
Matthew Naylor 2016-05-25 13:27:12 +01:00
parent 05c0808ff2
commit 213bb26367
1 changed files with 3 additions and 0 deletions
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groundtest/src/main/scala/tile.scala
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@ -144,6 +144,9 @@ class GroundTestTile(id: Int, resetSignal: Bool)
dcache.io.cpu <> dcacheIF.io.cache
io.cached.head <> dcache.io.mem
// SimpleHellaCacheIF leaves invalidate_lr dangling, so we wire it to false
dcache.io.cpu.invalidate_lr := Bool(false)
val ptw = Module(new DummyPTW(2))
ptw.io.requestors(0) <> test.io.ptw
ptw.io.requestors(1) <> dcache.io.ptw