From 213bb2636782bbb3b7d65a62fa9e1680735ad5ce Mon Sep 17 00:00:00 2001 From: Matthew Naylor Date: Wed, 25 May 2016 13:27:12 +0100 Subject: [PATCH] Drive invalidate_lr signal The DCache input for invalidating LR reservations was dangling. Now we wire it to false. --- groundtest/src/main/scala/tile.scala | 3 +++ 1 file changed, 3 insertions(+) diff --git a/groundtest/src/main/scala/tile.scala b/groundtest/src/main/scala/tile.scala index 616af87c..1ef17cc6 100644 --- a/groundtest/src/main/scala/tile.scala +++ b/groundtest/src/main/scala/tile.scala @@ -144,6 +144,9 @@ class GroundTestTile(id: Int, resetSignal: Bool) dcache.io.cpu <> dcacheIF.io.cache io.cached.head <> dcache.io.mem + // SimpleHellaCacheIF leaves invalidate_lr dangling, so we wire it to false + dcache.io.cpu.invalidate_lr := Bool(false) + val ptw = Module(new DummyPTW(2)) ptw.io.requestors(0) <> test.io.ptw ptw.io.requestors(1) <> dcache.io.ptw