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Merge pull request #1190 from freechipsproject/bus-api

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BusWrapper API Update
This commit is contained in:
Henry Cook
2018-03-01 01:13:50 -08:00
committed by GitHub
parent cdd2a9227f 30c0635bb3
commit 20a8876856
55 changed files with 749 additions and 672 deletions
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2
src/main/scala/tilelink/AsyncCrossing.scala
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@ -7,7 +7,7 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
import freechips.rocketchip.coreplex.{CrossingWrapper, AsynchronousCrossing}
import freechips.rocketchip.subsystem.{CrossingWrapper, AsynchronousCrossing}
class TLAsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{

85
src/main/scala/tilelink/Bus.scala
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@ -1,85 +0,0 @@
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
case object TLBusDelayProbability extends Field[Double](0.0)
/** Specifies widths of various attachement points in the SoC */
trait TLBusParams {
val beatBytes: Int
val blockBytes: Int
val masterBuffering: BufferParams
val slaveBuffering: BufferParams
def beatBits: Int = beatBytes * 8
def blockBits: Int = blockBytes * 8
def blockBeats: Int = blockBytes / beatBytes
def blockOffset: Int = log2Up(blockBytes)
}
abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p: Parameters)
extends SimpleLazyModule with LazyScope with TLBusParams {
val beatBytes = params.beatBytes
val blockBytes = params.blockBytes
val masterBuffering = params.masterBuffering
val slaveBuffering = params.slaveBuffering
require(blockBytes % beatBytes == 0)
private val delayProb = p(TLBusDelayProbability)
protected val xbar = LazyModule(new TLXbar)
xbar.suggestName(busName)
private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
master_buffer.suggestName(s"${busName}_master_TLBuffer")
private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
slave_buffer.suggestName(s"${busName}_slave_TLBuffer")
private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes))
slave_frag.suggestName(s"${busName}_slave_TLFragmenter")
private val slave_ww = LazyModule(new TLWidthWidget(beatBytes))
slave_ww.suggestName(s"${busName}_slave_TLWidthWidget")
private val delayedNode = if (delayProb > 0.0) {
val firstDelay = LazyModule(new TLDelayer(delayProb))
val flowDelay = LazyModule(new TLBuffer(BufferParams.flow))
val secondDelay = LazyModule(new TLDelayer(delayProb))
firstDelay.node :*= xbar.node
flowDelay.node :*= firstDelay.node
secondDelay.node :*= flowDelay.node
secondDelay.node
} else {
xbar.node
}
xbar.node :=* master_buffer.node
slave_buffer.node :*= delayedNode
slave_frag.node :*= slave_buffer.node
slave_ww.node :*= slave_buffer.node
protected def outwardNode: TLOutwardNode = delayedNode
protected def outwardBufNode: TLOutwardNode = slave_buffer.node
protected def outwardFragNode: TLOutwardNode = slave_frag.node
protected def outwardWWNode: TLOutwardNode = slave_ww.node
protected def inwardNode: TLInwardNode = xbar.node
protected def inwardBufNode: TLInwardNode = master_buffer.node
def bufferFromMasters: TLInwardNode = inwardBufNode
def bufferToSlaves: TLOutwardNode = outwardBufNode
def toSyncSlaves(name: Option[String] = None, addBuffers: Int = 0): TLOutwardNode = {
TLBuffer.chain(addBuffers).foldRight(outwardBufNode)(_ :*= _)
}
def toVariableWidthSlaves: TLOutwardNode = outwardFragNode
def toFixedWidthSlaves: TLOutwardNode = outwardWWNode
def toFixedWidthPorts: TLOutwardNode = outwardWWNode // TODO, do/don't buffer here; knowing we will after the necessary port conversions
}

87
src/main/scala/tilelink/BusWrapper.scala Normal file
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@ -0,0 +1,87 @@
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
case object TLBusDelayProbability extends Field[Double](0.0)
/** Specifies widths of various attachement points in the SoC */
trait HasTLBusParams {
val beatBytes: Int
val blockBytes: Int
def beatBits: Int = beatBytes * 8
def blockBits: Int = blockBytes * 8
def blockBeats: Int = blockBytes / beatBytes
def blockOffset: Int = log2Up(blockBytes)
}
abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implicit p: Parameters)
extends SimpleLazyModule with LazyScope with HasTLBusParams {
val beatBytes = params.beatBytes
val blockBytes = params.blockBytes
require(blockBytes % beatBytes == 0)
protected def inwardNode: TLInwardNode
protected def outwardNode: TLOutwardNode
protected def bufferFrom(buffer: BufferParams): TLInwardNode =
inwardNode :=* TLBuffer(buffer)
protected def bufferFrom(buffers: Int): TLInwardNode =
TLBuffer.chain(buffers).foldLeft(inwardNode)(_ :=* _)
protected def fixFrom(policy: TLFIFOFixer.Policy, buffers: Int): TLInwardNode =
inwardNode :=* TLBuffer.chain(buffers).foldLeft(TLFIFOFixer(policy))(_ :=* _)
protected def bufferTo(buffer: BufferParams): TLOutwardNode =
TLBuffer(buffer) :*= delayNode :*= outwardNode
protected def bufferTo(buffers: Int): TLOutwardNode =
TLBuffer.chain(buffers).foldRight(delayNode)(_ :*= _) :*= outwardNode
protected def fixedWidthTo(buffer: BufferParams): TLOutwardNode =
TLWidthWidget(beatBytes) :*= bufferTo(buffer)
protected def fragmentTo(buffer: BufferParams): TLOutwardNode =
TLFragmenter(beatBytes, blockBytes) :*= bufferTo(buffer)
protected def fragmentTo(minSize: Int, maxSize: Int, buffer: BufferParams): TLOutwardNode =
TLFragmenter(minSize, maxSize) :*= bufferTo(buffer)
protected def delayNode(implicit p: Parameters): TLNode = {
val delayProb = p(TLBusDelayProbability)
if (delayProb > 0.0) {
TLDelayer(delayProb) :*=* TLBuffer(BufferParams.flow) :*=* TLDelayer(delayProb)
} else {
val nodelay = TLIdentityNode()
nodelay
}
}
protected def to[T](name: String)(body: => T): T = {
this { LazyScope(s"coupler_to_${name}") { body } }
}
protected def from[T](name: String)(body: => T): T = {
this { LazyScope(s"coupler_from_${name}") { body } }
}
}
trait HasTLXbarPhy { this: TLBusWrapper =>
private val xbar = LazyModule(new TLXbar).suggestName(busName + "_xbar")
protected def inwardNode: TLInwardNode = xbar.node
protected def outwardNode: TLOutwardNode = xbar.node
}
object TLIdentity {
def gen: TLNode = {
val passthru = TLIdentityNode()
passthru
}
}

12
src/main/scala/tilelink/Nodes.scala
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@ -30,18 +30,6 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
pd.copy(clients = pd.clients.map { c => c.copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLManagerPortParameters, node: InwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle]): TLManagerPortParameters =
pu.copy(managers = pu.managers.map { m => m.copy (nodePath = node +: m.nodePath) })
override def getO(pu: TLManagerPortParameters): Option[BaseNode] = {
val head = pu.managers.map(_.nodePath.headOption)
if (head.exists(!_.isDefined) || head.map(_.get).distinct.size != 1) {
None
} else {
val subproblem = pu.copy(managers = pu.managers.map(m => m.copy(nodePath = m.nodePath.tail)))
getO(subproblem) match {
case Some(x) => Some(x)
case None => Some(head(0).get)
}
}
}
}
case class TLClientNode(portParams: Seq[TLClientPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams)