86 lines
3.0 KiB
Scala
86 lines
3.0 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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case object TLBusDelayProbability extends Field[Double](0.0)
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/** Specifies widths of various attachement points in the SoC */
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trait TLBusParams {
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val beatBytes: Int
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val blockBytes: Int
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val masterBuffering: BufferParams
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val slaveBuffering: BufferParams
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def beatBits: Int = beatBytes * 8
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def blockBits: Int = blockBytes * 8
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def blockBeats: Int = blockBytes / beatBytes
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def blockOffset: Int = log2Up(blockBytes)
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}
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abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p: Parameters)
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extends SimpleLazyModule with LazyScope with TLBusParams {
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val beatBytes = params.beatBytes
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val blockBytes = params.blockBytes
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val masterBuffering = params.masterBuffering
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val slaveBuffering = params.slaveBuffering
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require(blockBytes % beatBytes == 0)
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private val delayProb = p(TLBusDelayProbability)
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protected val xbar = LazyModule(new TLXbar)
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xbar.suggestName(busName)
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private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
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master_buffer.suggestName(s"${busName}_master_TLBuffer")
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private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
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slave_buffer.suggestName(s"${busName}_slave_TLBuffer")
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private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes))
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slave_frag.suggestName(s"${busName}_slave_TLFragmenter")
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private val slave_ww = LazyModule(new TLWidthWidget(beatBytes))
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slave_ww.suggestName(s"${busName}_slave_TLWidthWidget")
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private val delayedNode = if (delayProb > 0.0) {
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val firstDelay = LazyModule(new TLDelayer(delayProb))
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val flowDelay = LazyModule(new TLBuffer(BufferParams.flow))
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val secondDelay = LazyModule(new TLDelayer(delayProb))
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firstDelay.node :*= xbar.node
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flowDelay.node :*= firstDelay.node
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secondDelay.node :*= flowDelay.node
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secondDelay.node
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} else {
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xbar.node
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}
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xbar.node :=* master_buffer.node
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slave_buffer.node :*= delayedNode
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slave_frag.node :*= slave_buffer.node
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slave_ww.node :*= slave_buffer.node
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protected def outwardNode: TLOutwardNode = delayedNode
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protected def outwardBufNode: TLOutwardNode = slave_buffer.node
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protected def outwardFragNode: TLOutwardNode = slave_frag.node
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protected def outwardWWNode: TLOutwardNode = slave_ww.node
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protected def inwardNode: TLInwardNode = xbar.node
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protected def inwardBufNode: TLInwardNode = master_buffer.node
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def bufferFromMasters: TLInwardNode = inwardBufNode
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def bufferToSlaves: TLOutwardNode = outwardBufNode
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def toSyncSlaves(name: Option[String] = None, addBuffers: Int = 0): TLOutwardNode = {
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TLBuffer.chain(addBuffers).foldRight(outwardBufNode)(_ :*= _)
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}
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def toVariableWidthSlaves: TLOutwardNode = outwardFragNode
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def toFixedWidthSlaves: TLOutwardNode = outwardWWNode
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def toFixedWidthPorts: TLOutwardNode = outwardWWNode // TODO, do/don't buffer here; knowing we will after the necessary port conversions
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}
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