diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 023871e1..5c3365c2 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -296,6 +296,7 @@ class BaseConfig extends Config (
       case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
       case NTiles => Knob("NTILES")
       case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
+      case TMemoryChannels => BusType.AXI
       case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL")
       case NOutstandingMemReqsPerChannel => site(NBanksPerMemoryChannel)*(site(NAcquireTransactors)+2)
       case BankIdLSB => 0
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index e0e8ab12..d48ea879 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -11,8 +11,17 @@ import rocket.Util._
 
 /** Top-level parameters of RocketChip, values set in e.g. PublicConfigs.scala */
 
+/** Options for memory bus interface */
+object BusType {
+  sealed trait EnumVal
+  case object AXI extends EnumVal
+  case object AHB extends EnumVal
+  val busTypes = Seq(AXI, AHB)
+}
+
 /** Number of memory channels */
 case object NMemoryChannels extends Field[Int]
+case object TMemoryChannels extends Field[BusType.EnumVal]
 /** Number of banks per memory channel */
 case object NBanksPerMemoryChannel extends Field[Int]
 /** Least significant bit of address used for bank partitioning */