riscv/rocket-chip
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Make log more sensible for long-latency operations

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Show only one write to the destination register, not two.
This commit is contained in:
Andrew Waterman 2017-06-26 15:31:11 -07:00
parent 6f8fdff762
commit 2077e4190b
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/Rocket.scala
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@ -675,7 +675,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
else { else {
printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
io.hartid, csr.io.time(31,0), wb_valid, wb_reg_pc, io.hartid, csr.io.time(31,0), wb_valid, wb_reg_pc,
Mux(rf_wen, rf_waddr, UInt(0)), rf_wdata, rf_wen, Mux(rf_wen && !(wb_set_sboard && wb_wen), rf_waddr, UInt(0)), rf_wdata, rf_wen,
wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))), wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))), wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),
wb_reg_inst, wb_reg_inst) wb_reg_inst, wb_reg_inst)