From 2077e4190b1d4c287b7612b0a1bf54f8bfdaa8f9 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 26 Jun 2017 15:31:11 -0700 Subject: [PATCH] Make log more sensible for long-latency operations Show only one write to the destination register, not two. --- src/main/scala/rocket/Rocket.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/Rocket.scala b/src/main/scala/rocket/Rocket.scala index b143bcc5..a8189831 100644 --- a/src/main/scala/rocket/Rocket.scala +++ b/src/main/scala/rocket/Rocket.scala @@ -675,7 +675,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) else { printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, csr.io.time(31,0), wb_valid, wb_reg_pc, - Mux(rf_wen, rf_waddr, UInt(0)), rf_wdata, rf_wen, + Mux(rf_wen && !(wb_set_sboard && wb_wen), rf_waddr, UInt(0)), rf_wdata, rf_wen, wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))), wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))), wb_reg_inst, wb_reg_inst)