riscv/rocket-chip
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Fix SimpleHellaCacheIF assumption about receiving rejected request back 2 cycles later

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This commit is contained in:
jackkoenig 2015-11-08 21:16:31 -08:00
parent 2f515b2af6
commit 1e259a55da
1 changed files with 2 additions and 1 deletions
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3
rocket/src/main/scala/nbdcache.scala
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@ -751,6 +751,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val s1_clk_en = Reg(Bool()) val s1_clk_en = Reg(Bool())
val s2_valid = Reg(next=s1_valid_masked, init=Bool(false)) val s2_valid = Reg(next=s1_valid_masked, init=Bool(false))
val s2_killed = Reg(next=s1_valid && io.cpu.req.bits.kill)
val s2_req = Reg(io.cpu.req.bits) val s2_req = Reg(io.cpu.req.bits)
val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd != M_NOP val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd != M_NOP
val s2_recycle = Wire(Bool()) val s2_recycle = Wire(Bool())
@ -1053,7 +1054,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
uncache_resp.bits := mshrs.io.resp.bits uncache_resp.bits := mshrs.io.resp.bits
uncache_resp.valid := mshrs.io.resp.valid uncache_resp.valid := mshrs.io.resp.valid
val cache_pass = s2_valid || s2_replay val cache_pass = s2_valid || s2_killed || s2_replay
mshrs.io.resp.ready := !cache_pass mshrs.io.resp.ready := !cache_pass
io.cpu.resp := Mux(cache_pass, cache_resp, uncache_resp) io.cpu.resp := Mux(cache_pass, cache_resp, uncache_resp)