diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 2223ade0..2a4645c2 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -751,6 +751,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   val s1_clk_en = Reg(Bool())
 
   val s2_valid = Reg(next=s1_valid_masked, init=Bool(false))
+  val s2_killed = Reg(next=s1_valid && io.cpu.req.bits.kill)
   val s2_req = Reg(io.cpu.req.bits)
   val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd != M_NOP
   val s2_recycle = Wire(Bool())
@@ -1053,7 +1054,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   uncache_resp.bits := mshrs.io.resp.bits
   uncache_resp.valid := mshrs.io.resp.valid
 
-  val cache_pass = s2_valid || s2_replay
+  val cache_pass = s2_valid || s2_killed || s2_replay
   mshrs.io.resp.ready := !cache_pass
 
   io.cpu.resp := Mux(cache_pass, cache_resp, uncache_resp)