riscv/rocket-chip
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support testing RV32D configs

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This commit is contained in:
Andrew Waterman 2018-02-20 15:45:07 -08:00
parent d4fb7ad6a2
commit 1dc1e2c099
2 changed files with 7 additions and 9 deletions
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11
src/main/scala/system/Generator.scala
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@ -57,15 +57,14 @@ object Generator extends GeneratorApp {
val env = if (vm) List("p","v") else List("p")
coreParams.fpu foreach { case cfg =>
if (xlen == 32) {
TestGeneration.addSuites(env.map(rv32ufNoDiv))
TestGeneration.addSuites(env.map(rv32uf))
if (cfg.fLen >= 64)
TestGeneration.addSuites(env.map(rv32ud))
} else {
TestGeneration.addSuite(rv32udBenchmarks)
TestGeneration.addSuites(env.map(rv64ufNoDiv))
TestGeneration.addSuites(env.map(rv64udNoDiv))
if (cfg.divSqrt) {
TestGeneration.addSuites(env.map(rv64uf))
TestGeneration.addSuites(env.map(rv64uf))
if (cfg.fLen >= 64)
TestGeneration.addSuites(env.map(rv64ud))
}
}
}
if (coreParams.useAtomics) {

5
src/main/scala/system/RocketTestSuite.scala
View File

@ -143,13 +143,12 @@ object DefaultTestSuites {
val rv64ufNames = LinkedHashSet("ldst", "move", "fcmp", "fcvt", "fcvt_w", "fclass", "fadd", "fdiv", "fmin", "fmadd")
val rv64uf = new AssemblyTestSuite("rv64uf", rv64ufNames)(_)
val rv64ufNoDiv = new AssemblyTestSuite("rv64uf", rv64ufNames - "fdiv")(_)
val rv32ufNoDiv = new AssemblyTestSuite("rv32uf", rv64ufNames - "fdiv")(_)
val rv32uf = new AssemblyTestSuite("rv32uf", rv64ufNames)(_)
val rv32ud = new AssemblyTestSuite("rv32ud", rv64ufNames - "move")(_)
val rv64udNames = rv64ufNames + "structural"
val rv64ud = new AssemblyTestSuite("rv64ud", rv64udNames)(_)
val rv64udNoDiv = new AssemblyTestSuite("rv64ud", rv64udNames - "fdiv")(_)
val rv64siNames = rv32siNames
val rv64si = new AssemblyTestSuite("rv64si", rv64siNames)(_)