support testing RV32D configs
This commit is contained in:
parent
d4fb7ad6a2
commit
1dc1e2c099
@ -57,17 +57,16 @@ object Generator extends GeneratorApp {
|
|||||||
val env = if (vm) List("p","v") else List("p")
|
val env = if (vm) List("p","v") else List("p")
|
||||||
coreParams.fpu foreach { case cfg =>
|
coreParams.fpu foreach { case cfg =>
|
||||||
if (xlen == 32) {
|
if (xlen == 32) {
|
||||||
TestGeneration.addSuites(env.map(rv32ufNoDiv))
|
TestGeneration.addSuites(env.map(rv32uf))
|
||||||
|
if (cfg.fLen >= 64)
|
||||||
|
TestGeneration.addSuites(env.map(rv32ud))
|
||||||
} else {
|
} else {
|
||||||
TestGeneration.addSuite(rv32udBenchmarks)
|
TestGeneration.addSuite(rv32udBenchmarks)
|
||||||
TestGeneration.addSuites(env.map(rv64ufNoDiv))
|
|
||||||
TestGeneration.addSuites(env.map(rv64udNoDiv))
|
|
||||||
if (cfg.divSqrt) {
|
|
||||||
TestGeneration.addSuites(env.map(rv64uf))
|
TestGeneration.addSuites(env.map(rv64uf))
|
||||||
|
if (cfg.fLen >= 64)
|
||||||
TestGeneration.addSuites(env.map(rv64ud))
|
TestGeneration.addSuites(env.map(rv64ud))
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
|
||||||
if (coreParams.useAtomics) {
|
if (coreParams.useAtomics) {
|
||||||
if (tileParams.dcache.flatMap(_.scratch).isEmpty)
|
if (tileParams.dcache.flatMap(_.scratch).isEmpty)
|
||||||
TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
|
TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
|
||||||
|
@ -143,13 +143,12 @@ object DefaultTestSuites {
|
|||||||
|
|
||||||
val rv64ufNames = LinkedHashSet("ldst", "move", "fcmp", "fcvt", "fcvt_w", "fclass", "fadd", "fdiv", "fmin", "fmadd")
|
val rv64ufNames = LinkedHashSet("ldst", "move", "fcmp", "fcvt", "fcvt_w", "fclass", "fadd", "fdiv", "fmin", "fmadd")
|
||||||
val rv64uf = new AssemblyTestSuite("rv64uf", rv64ufNames)(_)
|
val rv64uf = new AssemblyTestSuite("rv64uf", rv64ufNames)(_)
|
||||||
val rv64ufNoDiv = new AssemblyTestSuite("rv64uf", rv64ufNames - "fdiv")(_)
|
|
||||||
|
|
||||||
val rv32ufNoDiv = new AssemblyTestSuite("rv32uf", rv64ufNames - "fdiv")(_)
|
val rv32uf = new AssemblyTestSuite("rv32uf", rv64ufNames)(_)
|
||||||
|
val rv32ud = new AssemblyTestSuite("rv32ud", rv64ufNames - "move")(_)
|
||||||
|
|
||||||
val rv64udNames = rv64ufNames + "structural"
|
val rv64udNames = rv64ufNames + "structural"
|
||||||
val rv64ud = new AssemblyTestSuite("rv64ud", rv64udNames)(_)
|
val rv64ud = new AssemblyTestSuite("rv64ud", rv64udNames)(_)
|
||||||
val rv64udNoDiv = new AssemblyTestSuite("rv64ud", rv64udNames - "fdiv")(_)
|
|
||||||
|
|
||||||
val rv64siNames = rv32siNames
|
val rv64siNames = rv32siNames
|
||||||
val rv64si = new AssemblyTestSuite("rv64si", rv64siNames)(_)
|
val rv64si = new AssemblyTestSuite("rv64si", rv64siNames)(_)
|
||||||
|
Loading…
Reference in New Issue
Block a user