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shiftReg: Make it so that register '0' is always closest to the q output, regardless of the type of shift register created.

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This commit is contained in:
Megan Wachs 2017-09-07 09:51:46 -07:00
parent dcafb5fea3
commit 1da6cb85ab
1 changed files with 8 additions and 7 deletions
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5
src/main/scala/util/ShiftReg.scala
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@ -9,7 +9,8 @@ import Chisel._
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldLeft(in) {
(0 until n).foldRight(in) {
case (next, i) => {
val r = Reg(next, next = next, init = init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
@ -51,7 +52,7 @@ object AbstractPipelineReg {
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
require(depth >= 0, "Depth must be greater than or equal to 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"