From 1da6cb85aba287f0bce48dfcb38cc18ded1f5cc7 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 7 Sep 2017 09:51:46 -0700
Subject: [PATCH] shiftReg: Make it so that register '0' is always closest to
 the q output, regardless of the type of shift register created.

---
 src/main/scala/util/ShiftReg.scala | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/util/ShiftReg.scala b/src/main/scala/util/ShiftReg.scala
index 3f9d3e44..204d8195 100644
--- a/src/main/scala/util/ShiftReg.scala
+++ b/src/main/scala/util/ShiftReg.scala
@@ -9,13 +9,14 @@ import Chisel._
 // to provide a reset value.
 object ShiftRegInit {
   def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
-    (0 until n).foldLeft(in) {
-      case (next, i) => {
-        val r = Reg(next, next = next, init = init)
-        name.foreach { na => r.suggestName(s"${na}_${i}") }
-        r
-      }
+
+  (0 until n).foldRight(in) {
+    case (next, i) => {
+      val r = Reg(next, next = next, init = init)
+      name.foreach { na => r.suggestName(s"${na}_${i}") }
+      r
     }
+  }
 }
 
 /** These wrap behavioral
@@ -51,7 +52,7 @@ object AbstractPipelineReg {
 }
 
 class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
-  require(depth > 0, "Depth must be greater than 0.")
+  require(depth >= 0, "Depth must be greater than or equal to 0.")
 
   override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"