add LICENSE

LICENSE

@@ -0,0 +1,24 @@
+Copyright (c) 2012-2014, The Regents of the University of California
+(Regents).  All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+1. Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+3. Neither the name of the Regents nor the
+   names of its contributors may be used to endorse or promote products
+   derived from this software without specific prior written permission.
+
+IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
+SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
+BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
+HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
+MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.

README.md

@@ -1,3 +1,19 @@
+Rocket Chip Generator
+=====================
+
+This repository contains the Rocket chip generator necessary to instantiate
+the RISC-V Rocket Core.
+
+Contributors
+------------
+
+Scott Beamer
+Henry Cook
+Yunsup Lee
+Stephen Twigg
+Huy Vo
+Andrew Waterman
+
 _Quick and dirty instructions:_
 
 Checkout The Code

csrc/emulator.cc

@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #include "htif_emulator.h"
 #include "emulator.h"
 #include "mm.h"

csrc/htif_emulator.h

@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #ifndef _HTIF_EMULATOR_H
 #define _HTIF_EMULATOR_H
 

csrc/mm.cc

@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #include "mm.h"
 #include <iostream>
 #include <fstream>

csrc/mm.h

@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #ifndef MM_EMULATOR_H
 #define MM_EMULATOR_H
 

csrc/mm_dramsim2.cc

@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #include "mm_dramsim2.h"
 #include "mm.h"
 #include <DRAMSim.h>

csrc/mm_dramsim2.h

@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #ifndef _MM_EMULATOR_DRAMSIM2_H
 #define _MM_EMULATOR_DRAMSIM2_H
 

csrc/vcs_main.cc

@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #include "htif_emulator.h"
 #include "mm.h"
 #include "mm_dramsim2.h"

fsim/fpga_mem_gen

@@ -1,9 +1,11 @@
 #! /usr/bin/env python
+
+# See LICENSE for license details.
+# This is based off of reference-chip/vlsi/src/vlsi_mem_gen
+
 import sys
 import math
 
-# This is based off of reference-chip/vlsi/src/vlsi_mem_gen
-
 use_latches = 1
 
 

src/main/scala/Backends.scala

@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 package rocketchip
 
 import Chisel._

src/main/scala/PublicConfigs.scala

@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 package rocketchip
 
 import Chisel._

src/main/scala/RocketChip.scala

@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 package rocketchip
 
 import Chisel._

src/main/scala/network.scala

@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 package rocketchip
 
 import Chisel._

src/main/scala/vlsi.scala

@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 package rocketchip
 
 import Chisel._

vsim/vlsi_mem_gen

@@ -1,4 +1,7 @@
 #! /usr/bin/env python
+
+# See LICENSE for license details.
+
 import sys
 import math
 

vsrc/backup_mem.v

@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 `define ceilLog2(x) ( \
 (x) > 2**30 ? 31 : \
 (x) > 2**29 ? 30 : \

vsrc/rocketTestHarness.v

@@ -1,4 +1,4 @@
-// Test harness for Rocket RISC-V Processor
+// See LICENSE for license details.
 
 extern "A" void htif_init
 (