117 lines
2.8 KiB
Verilog
117 lines
2.8 KiB
Verilog
// See LICENSE for license details.
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`define ceilLog2(x) ( \
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(x) > 2**30 ? 31 : \
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(x) > 2**29 ? 30 : \
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(x) > 2**28 ? 29 : \
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(x) > 2**27 ? 28 : \
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(x) > 2**26 ? 27 : \
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(x) > 2**25 ? 26 : \
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(x) > 2**24 ? 25 : \
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(x) > 2**23 ? 24 : \
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(x) > 2**22 ? 23 : \
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(x) > 2**21 ? 22 : \
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(x) > 2**20 ? 21 : \
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(x) > 2**19 ? 20 : \
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(x) > 2**18 ? 19 : \
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(x) > 2**17 ? 18 : \
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(x) > 2**16 ? 17 : \
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(x) > 2**15 ? 16 : \
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(x) > 2**14 ? 15 : \
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(x) > 2**13 ? 14 : \
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(x) > 2**12 ? 13 : \
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(x) > 2**11 ? 12 : \
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(x) > 2**10 ? 11 : \
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(x) > 2**9 ? 10 : \
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(x) > 2**8 ? 9 : \
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(x) > 2**7 ? 8 : \
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(x) > 2**6 ? 7 : \
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(x) > 2**5 ? 6 : \
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(x) > 2**4 ? 5 : \
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(x) > 2**3 ? 4 : \
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(x) > 2**2 ? 3 : \
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(x) > 2**1 ? 2 : \
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(x) > 2**0 ? 1 : 0)
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`ifdef MEM_BACKUP_EN
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module BackupMemory
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(
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input clk,
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input reset,
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input mem_req_valid,
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output mem_req_ready,
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input mem_req_rw,
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input [`MEM_ADDR_BITS-1:0] mem_req_addr,
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input [`MEM_TAG_BITS-1:0] mem_req_tag,
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input mem_req_data_valid,
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output mem_req_data_ready,
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input [`MEM_DATA_BITS-1:0] mem_req_data_bits,
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output reg mem_resp_valid,
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output reg [`MEM_DATA_BITS-1:0] mem_resp_data,
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output reg [`MEM_TAG_BITS-1:0] mem_resp_tag
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);
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localparam DATA_CYCLES = 4;
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localparam DEPTH = 2*1024*1024;
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reg [`ceilLog2(DATA_CYCLES)-1:0] cnt;
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reg [`MEM_TAG_BITS-1:0] tag;
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reg state_busy, state_rw;
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reg [`MEM_ADDR_BITS-1:0] addr;
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reg [`MEM_DATA_BITS-1:0] ram [DEPTH-1:0];
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wire [`ceilLog2(DEPTH)-1:0] ram_addr = state_busy ? {addr[`ceilLog2(DEPTH/DATA_CYCLES)-1:0], cnt}
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: {mem_req_addr[`ceilLog2(DEPTH/DATA_CYCLES)-1:0], cnt};
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wire do_read = mem_req_valid && mem_req_ready && !mem_req_rw || state_busy && !state_rw;
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wire do_write = mem_req_data_valid && mem_req_data_ready;
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initial
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begin : zero
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integer i;
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for (i = 0; i < DEPTH; i = i+1)
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ram[i] = 1'b0;
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end
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always @(posedge clk)
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begin
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if (reset)
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state_busy <= 1'b0;
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else if ((do_read || do_write) && cnt == DATA_CYCLES-1)
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state_busy <= 1'b0;
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else if (mem_req_valid && mem_req_ready)
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state_busy <= 1'b1;
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if (!state_busy && mem_req_valid)
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begin
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state_rw <= mem_req_rw;
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tag <= mem_req_tag;
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addr <= mem_req_addr;
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end
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if (reset)
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cnt <= 1'b0;
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else if(do_read || do_write)
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cnt <= cnt + 1'b1;
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if (do_write)
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ram[ram_addr] <= mem_req_data_bits;
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else
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mem_resp_data <= ram[ram_addr];
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if (reset)
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mem_resp_valid <= 1'b0;
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else
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mem_resp_valid <= do_read;
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mem_resp_tag <= state_busy ? tag : mem_req_tag;
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end
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assign mem_req_ready = !state_busy;
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assign mem_req_data_ready = state_busy && state_rw;
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endmodule
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`endif
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