From 1cb65d5ec1075f70dd68c21bd4b4e8eecee86b02 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 29 Dec 2014 22:56:18 -0800 Subject: [PATCH] %s/master/manager/g --- rocket/src/main/scala/icache.scala | 2 +- rocket/src/main/scala/nbdcache.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index e9b1671c..63b1ec74 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -253,7 +253,7 @@ class ICache extends FrontendModule val ack_q = Module(new Queue(new LogicalNetworkIO(new Finish), 1)) ack_q.io.enq.valid := refill_done && co.requiresAckForGrant(refill_bits.payload) - ack_q.io.enq.bits.payload.master_xact_id := refill_bits.payload.master_xact_id + ack_q.io.enq.bits.payload.manager_xact_id := refill_bits.payload.manager_xact_id ack_q.io.enq.bits.header.dst := refill_bits.header.src // output signals diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index dccdf7a4..7fa3044c 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -260,7 +260,7 @@ class MSHR(id: Int) extends L1HellaCacheModule { val ackq = Module(new Queue(new LogicalNetworkIO(new Finish), 1)) ackq.io.enq.valid := (wb_done || refill_done) && co.requiresAckForGrant(io.mem_grant.bits.payload) - ackq.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id + ackq.io.enq.bits.payload.manager_xact_id := io.mem_grant.bits.payload.manager_xact_id ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp io.mem_finish.valid := ackq.io.deq.valid && can_finish