From 1cb2d1d7b7191aff8f8004b9b64a5d908c96fd6b Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Thu, 4 Sep 2014 11:06:01 -0700 Subject: [PATCH] initialize all SRAMs to avoid X propagation problem --- fsim/fpga_mem_gen | 8 ++++++++ vsim/vlsi_mem_gen | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/fsim/fpga_mem_gen b/fsim/fpga_mem_gen index 80d8b6aa..f8aa5578 100755 --- a/fsim/fpga_mem_gen +++ b/fsim/fpga_mem_gen @@ -122,6 +122,14 @@ def gen_mem(name, width, depth, ports, mask_gran): sys.exit('%s: unknown port type %s' % (sys.argv[0], ptype)) decl += ['reg [%d:0] ram [%d:0];' % (width-1, depth-1)] + decl += ['`ifndef SYNTHESIS'] + decl += [' integer initvar;'] + decl += [' initial begin'] + decl += [' #0.002;'] + decl += [' for (initvar = 0; initvar < %d; initvar = initvar+1)' % depth] + decl += [' ram[initvar] = {%d {$random}};' % ((width-1)/32+1)] + decl += [' end'] + decl += ['`endif'] for pid in readports: decl += ['reg [%d:0] reg_R%dA;' % (addr_width-1, pid)] diff --git a/vsim/vlsi_mem_gen b/vsim/vlsi_mem_gen index 0366594e..de3c05ee 100755 --- a/vsim/vlsi_mem_gen +++ b/vsim/vlsi_mem_gen @@ -55,6 +55,14 @@ def gen_mem(name, width, depth, ports): tup = (depth, width, nr, nw, nrw, masked) decl.append('reg [%d:0] ram [%d:0];' % (width-1, depth-1)) + decl.append('`ifndef SYNTHESIS') + decl.append(' integer initvar;') + decl.append(' initial begin') + decl.append(' #0.002;') + decl.append(' for (initvar = 0; initvar < %d; initvar = initvar+1)' % depth) + decl.append(' ram[initvar] = {%d {$random}};' % ((width-1)/32+1)) + decl.append(' end') + decl.append('`endif') for pid in readports: decl.append('reg [%d:0] reg_R%dA;' % (addr_width-1, pid))