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ahb: backport to chisel2

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Merges #16
This commit is contained in:
Wesley W. Terpstra 2016-05-25 11:01:59 -07:00 committed by Andrew Waterman
parent a9599302bd
commit 1c8745dfd2
1 changed files with 4 additions and 1 deletions
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5
junctions/src/main/scala/hasti.scala
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@ -459,10 +459,13 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p)
// The mask and address during the address phase // The mask and address during the address phase
val a_request = io.hsel && (io.htrans === HTRANS_NONSEQ || io.htrans === HTRANS_SEQ) val a_request = io.hsel && (io.htrans === HTRANS_NONSEQ || io.htrans === HTRANS_SEQ)
val a_mask = mask_shift(hastiDataBytes-1, 0) val a_mask = Wire(UInt(width = hastiDataBytes))
val a_address = io.haddr >> UInt(hastiAlignment) val a_address = io.haddr >> UInt(hastiAlignment)
val a_write = io.hwrite val a_write = io.hwrite
// for backwards compatibility with chisel2, we needed a static width in definition
a_mask := mask_shift(hastiDataBytes-1, 0)
// The data phase signals // The data phase signals
val d_read = RegEnable(a_request && !a_write, Bool(false), ready) val d_read = RegEnable(a_request && !a_write, Bool(false), ready)
val d_mask = RegEnable(a_mask, ready && a_request) val d_mask = RegEnable(a_mask, ready && a_request)