From 1c8745dfd21d90b0f38399f98be54cb1fc371d56 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 25 May 2016 11:01:59 -0700 Subject: [PATCH] ahb: backport to chisel2 Merges #16 --- junctions/src/main/scala/hasti.scala | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/junctions/src/main/scala/hasti.scala b/junctions/src/main/scala/hasti.scala index 53637419..12bc86c7 100644 --- a/junctions/src/main/scala/hasti.scala +++ b/junctions/src/main/scala/hasti.scala @@ -459,9 +459,12 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p) // The mask and address during the address phase val a_request = io.hsel && (io.htrans === HTRANS_NONSEQ || io.htrans === HTRANS_SEQ) - val a_mask = mask_shift(hastiDataBytes-1, 0) + val a_mask = Wire(UInt(width = hastiDataBytes)) val a_address = io.haddr >> UInt(hastiAlignment) val a_write = io.hwrite + + // for backwards compatibility with chisel2, we needed a static width in definition + a_mask := mask_shift(hastiDataBytes-1, 0) // The data phase signals val d_read = RegEnable(a_request && !a_write, Bool(false), ready)