riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Make parameters for TLToAHB and TLToAXI4 accessable (#581)

Browse Source
This commit is contained in:
Jacob Chang
2017-03-10 22:26:38 -08:00
committed by GitHub
parent 43dea38ee9
commit 1c6dde8c15
2 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/uncore/tilelink2/ToAXI4.scala
View File

@ -35,7 +35,7 @@ case class TLToAXI4Node(idBits: Int) extends MixedAdapterNode(TLImp, AXI4Imp)(
minLatency = p.minLatency)
})
class TLToAXI4(idBits: Int, combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
class TLToAXI4(val idBits: Int, val combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
{
val node = TLToAXI4Node(idBits)