From 1c6dde8c15c7aca3bb98c650c65becbce62784bf Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Fri, 10 Mar 2017 22:26:38 -0800 Subject: [PATCH] Make parameters for TLToAHB and TLToAXI4 accessable (#581) --- src/main/scala/uncore/tilelink2/ToAHB.scala | 2 +- src/main/scala/uncore/tilelink2/ToAXI4.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/ToAHB.scala b/src/main/scala/uncore/tilelink2/ToAHB.scala index 7757c012..5be1a5dc 100644 --- a/src/main/scala/uncore/tilelink2/ToAHB.scala +++ b/src/main/scala/uncore/tilelink2/ToAHB.scala @@ -30,7 +30,7 @@ case class TLToAHBNode() extends MixedAdapterNode(TLImp, AHBImp)( TLManagerPortParameters(managers, beatBytes, 1, 1) }) -class TLToAHB(combinational: Boolean = true)(implicit p: Parameters) extends LazyModule +class TLToAHB(val combinational: Boolean = true)(implicit p: Parameters) extends LazyModule { val node = TLToAHBNode() diff --git a/src/main/scala/uncore/tilelink2/ToAXI4.scala b/src/main/scala/uncore/tilelink2/ToAXI4.scala index 566013d9..8cfb311e 100644 --- a/src/main/scala/uncore/tilelink2/ToAXI4.scala +++ b/src/main/scala/uncore/tilelink2/ToAXI4.scala @@ -35,7 +35,7 @@ case class TLToAXI4Node(idBits: Int) extends MixedAdapterNode(TLImp, AXI4Imp)( minLatency = p.minLatency) }) -class TLToAXI4(idBits: Int, combinational: Boolean = true)(implicit p: Parameters) extends LazyModule +class TLToAXI4(val idBits: Int, val combinational: Boolean = true)(implicit p: Parameters) extends LazyModule { val node = TLToAXI4Node(idBits)