diff --git a/src/main/scala/uncore/tilelink2/ToAHB.scala b/src/main/scala/uncore/tilelink2/ToAHB.scala
index 7757c012..5be1a5dc 100644
--- a/src/main/scala/uncore/tilelink2/ToAHB.scala
+++ b/src/main/scala/uncore/tilelink2/ToAHB.scala
@@ -30,7 +30,7 @@ case class TLToAHBNode() extends MixedAdapterNode(TLImp, AHBImp)(
     TLManagerPortParameters(managers, beatBytes, 1, 1)
   })
 
-class TLToAHB(combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
+class TLToAHB(val combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
 {
   val node = TLToAHBNode()
 
diff --git a/src/main/scala/uncore/tilelink2/ToAXI4.scala b/src/main/scala/uncore/tilelink2/ToAXI4.scala
index 566013d9..8cfb311e 100644
--- a/src/main/scala/uncore/tilelink2/ToAXI4.scala
+++ b/src/main/scala/uncore/tilelink2/ToAXI4.scala
@@ -35,7 +35,7 @@ case class TLToAXI4Node(idBits: Int) extends MixedAdapterNode(TLImp, AXI4Imp)(
       minLatency = p.minLatency)
   })
 
-class TLToAXI4(idBits: Int, combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
+class TLToAXI4(val idBits: Int, val combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
 {
   val node = TLToAXI4Node(idBits)