riscv/rocket-chip
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Fixed bug regarding case sensitivity regarding ioICache,ioDCache

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This commit is contained in:
Christopher Celio 2012-02-07 14:07:42 -08:00
parent fde8e3b696
commit 1be9d15944
4 changed files with 12 additions and 12 deletions
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8
rocket/src/main/scala/arbiter.scala
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@ -20,8 +20,8 @@ class ioMem() extends Bundle
class ioMemArbiter extends Bundle() { class ioMemArbiter extends Bundle() {
val mem = new ioMem(); val mem = new ioMem();
val dcache = new ioDcache(); val dcache = new ioDCache();
// val icache = new ioIcache(); // val icache = new ioICache();
val icache = new ioIPrefetcherMem().flip(); val icache = new ioIPrefetcherMem().flip();
} }
@ -35,10 +35,10 @@ class rocketMemArbiter extends Component {
// Memory request is valid if either icache or dcache have a valid request // Memory request is valid if either icache or dcache have a valid request
io.mem.req_val := (io.icache.req_val || io.dcache.req_val); io.mem.req_val := (io.icache.req_val || io.dcache.req_val);
// Set read/write bit. Icache always reads // Set read/write bit. ICache always reads
io.mem.req_rw := Mux(io.dcache.req_val, io.dcache.req_rw, Bool(false)); io.mem.req_rw := Mux(io.dcache.req_val, io.dcache.req_rw, Bool(false));
// Give priority to Icache // Give priority to ICache
io.mem.req_addr := Mux(io.dcache.req_val, io.dcache.req_addr, io.icache.req_addr); io.mem.req_addr := Mux(io.dcache.req_val, io.dcache.req_addr, io.icache.req_addr);
// low bit of tag=0 for I$, 1 for D$ // low bit of tag=0 for I$, 1 for D$

6
rocket/src/main/scala/dcache.scala
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@ -28,7 +28,7 @@ class ioDmem(view: List[String] = null) extends Bundle(view) {
} }
// interface between D$ and next level in memory hierarchy // interface between D$ and next level in memory hierarchy
class ioDcache(view: List[String] = null) extends Bundle(view) { class ioDCache(view: List[String] = null) extends Bundle(view) {
val req_addr = UFix(PADDR_BITS - OFFSET_BITS, INPUT); val req_addr = UFix(PADDR_BITS - OFFSET_BITS, INPUT);
val req_tag = UFix(DMEM_TAG_BITS, INPUT); val req_tag = UFix(DMEM_TAG_BITS, INPUT);
val req_val = Bool(INPUT); val req_val = Bool(INPUT);
@ -42,12 +42,12 @@ class ioDcache(view: List[String] = null) extends Bundle(view) {
class ioDCacheDM extends Bundle() { class ioDCacheDM extends Bundle() {
val cpu = new ioDmem(); val cpu = new ioDmem();
val mem = new ioDcache().flip(); val mem = new ioDCache().flip();
} }
class ioDCacheHella extends Bundle() { class ioDCacheHella extends Bundle() {
val cpu = new ioDmem(); val cpu = new ioDmem();
val mem = new ioDcache().flip(); val mem = new ioDCache().flip();
} }
class rocketDCacheStoreGen extends Component { class rocketDCacheStoreGen extends Component {

8
rocket/src/main/scala/icache.scala
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@ -18,7 +18,7 @@ class ioImem(view: List[String] = null) extends Bundle (view)
} }
// interface between I$ and memory (128 bits wide) // interface between I$ and memory (128 bits wide)
class ioIcache(view: List[String] = null) extends Bundle (view) class ioICache(view: List[String] = null) extends Bundle (view)
{ {
val req_addr = UFix(PADDR_BITS - OFFSET_BITS, INPUT); val req_addr = UFix(PADDR_BITS - OFFSET_BITS, INPUT);
val req_val = Bool(INPUT); val req_val = Bool(INPUT);
@ -27,10 +27,10 @@ class ioIcache(view: List[String] = null) extends Bundle (view)
val resp_val = Bool(OUTPUT); val resp_val = Bool(OUTPUT);
} }
class ioICache extends Bundle() class ioRocketICache extends Bundle()
{ {
val cpu = new ioImem(); val cpu = new ioImem();
val mem = new ioIcache().flip(); val mem = new ioICache().flip();
} }
// basic direct mapped instruction cache // basic direct mapped instruction cache
@ -38,7 +38,7 @@ class ioICache extends Bundle()
// parameters : // parameters :
// lines = # cache lines // lines = # cache lines
class rocketICache(sets: Int, assoc: Int) extends Component { class rocketICache(sets: Int, assoc: Int) extends Component {
val io = new ioICache(); val io = new ioRocketICache();
val lines = sets * assoc; val lines = sets * assoc;
val addrbits = PADDR_BITS; val addrbits = PADDR_BITS;

2
rocket/src/main/scala/icache_prefetch.scala
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@ -17,7 +17,7 @@ class ioIPrefetcherMem(view: List[String] = null) extends Bundle (view)
} }
class ioIPrefetcher extends Bundle() { class ioIPrefetcher extends Bundle() {
val icache = new ioIcache(); val icache = new ioICache();
val mem = new ioIPrefetcherMem(); val mem = new ioIPrefetcherMem();
} }