riscv/rocket-chip
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Fixed bug regarding case sensitivity regarding ioICache,ioDCache

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This commit is contained in:
Christopher Celio committed 2012-02-07 14:07:42 -08:00
1 parent fde8e3b696
commit 1be9d15944
4 files changed
+12 -12
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rocket/src/main/scala/dcache.scala
+3 -3
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@@ -28,7 +28,7 @@ class ioDmem(view: List[String] = null) extends Bundle(view) {
}
// interface between D$ and next level in memory hierarchy
class ioDcache(view: List[String] = null) extends Bundle(view) {
class ioDCache(view: List[String] = null) extends Bundle(view) {
val req_addr = UFix(PADDR_BITS - OFFSET_BITS, INPUT);
val req_tag = UFix(DMEM_TAG_BITS, INPUT);
val req_val = Bool(INPUT);
@@ -42,12 +42,12 @@ class ioDcache(view: List[String] = null) extends Bundle(view) {
class ioDCacheDM extends Bundle() {
val cpu = new ioDmem();
val mem = new ioDcache().flip();
val mem = new ioDCache().flip();
}
class ioDCacheHella extends Bundle() {
val cpu = new ioDmem();
val mem = new ioDcache().flip();
val mem = new ioDCache().flip();
}
class rocketDCacheStoreGen extends Component {