020fbe8be9
This makes it posisble to use Parameters to control Monitors. However, we need to make all LazyModules carry Parameters.
99 lines
2.9 KiB
Scala
99 lines
2.9 KiB
Scala
// See LICENSE.SiFive for license details.
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package uncore.devices
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import Chisel._
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import junctions._
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import junctions.NastiConstants._
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import regmapper._
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import diplomacy._
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import uncore.tilelink2._
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import uncore.util._
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import util._
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import scala.math.{min,max}
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import config._
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/** Number of tiles */
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case object NTiles extends Field[Int]
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class CoreplexLocalInterrupts extends Bundle {
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val mtip = Bool()
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val msip = Bool()
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}
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object ClintConsts
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{
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def msipOffset(hart: Int) = hart * msipBytes
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def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes
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def timeOffset = 0xbff8
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def msipBytes = 4
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def timecmpBytes = 8
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def size = 0x10000
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}
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trait MixCoreplexLocalInterrupterParameters {
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implicit val p: Parameters
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}
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trait CoreplexLocalInterrupterBundle extends Bundle with MixCoreplexLocalInterrupterParameters {
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val tiles = Vec(p(NTiles), new CoreplexLocalInterrupts).asOutput
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val rtcTick = Bool(INPUT)
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}
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trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCoreplexLocalInterrupterParameters {
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val io: CoreplexLocalInterrupterBundle
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val address: AddressSet
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val timeWidth = 64
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val regWidth = 32
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val time = Seq.fill(timeWidth/regWidth)(Reg(init=UInt(0, width = regWidth)))
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when (io.rtcTick) {
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val newTime = time.asUInt + UInt(1)
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for ((reg, i) <- time zip (0 until timeWidth by regWidth))
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reg := newTime >> i
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}
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val timecmp = Seq.fill(p(NTiles)) { Seq.fill(timeWidth/regWidth)(Reg(UInt(width = regWidth))) }
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val ipi = Seq.fill(p(NTiles)) { RegInit(UInt(0, width = 1)) }
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for ((tile, i) <- io.tiles zipWithIndex) {
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tile.msip := ipi(i)(0)
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tile.mtip := time.asUInt >= timecmp(i).asUInt
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}
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/* 0000 msip hart 0
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* 0004 msip hart 1
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* 4000 mtimecmp hart 0 lo
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* 4004 mtimecmp hart 0 hi
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* 4008 mtimecmp hart 1 lo
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* 400c mtimecmp hart 1 hi
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* bff8 mtime lo
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* bffc mtime hi
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*/
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regmap(
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0 -> makeRegFields(ipi),
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ClintConsts.timecmpOffset(0) -> makeRegFields(timecmp.flatten),
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ClintConsts.timeOffset -> makeRegFields(time))
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def makeRegFields(s: Seq[UInt]) = s.map(r => RegField(regWidth, r))
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}
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/** Power, Reset, Clock, Interrupt */
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// Magic TL2 Incantation to create a TL2 Slave
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class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit p: Parameters)
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extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = true)(
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new TLRegBundle((), _) with CoreplexLocalInterrupterBundle)(
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new TLRegModule((), _, _) with CoreplexLocalInterrupterModule)
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{
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val globalConfigString = Seq(
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s"rtc {\n",
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s" addr 0x${(address + ClintConsts.timeOffset).toString(16)};\n",
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s"};\n").mkString
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val hartConfigStrings = (0 until p(NTiles)).map { i => Seq(
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s" timecmp 0x${(address + ClintConsts.timecmpOffset(i)).toString(16)};\n",
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s" ipi 0x${(address + ClintConsts.msipOffset(i)).toString(16)};\n").mkString
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}
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}
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