riscv/rocket-chip
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Removed has_data fields from all coherence messages, increased message type names to compensate

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Henry Cook
2012-03-02 23:51:53 -08:00
parent 35f97bf858
commit 1b3307df32
6 changed files with 73 additions and 55 deletions
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33
rocket/src/main/scala/consts.scala
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@ -191,16 +191,31 @@ object Constants
val GLOBAL_XACT_ID_BITS = 4
val NGLOBAL_XACTS = 1 << GLOBAL_XACT_ID_BITS
val TTYPE_BITS = 2
val X_READ_SHARED = UFix(0, TTYPE_BITS)
val X_READ_EXCLUSIVE = UFix(1, TTYPE_BITS)
val X_READ_UNCACHED = UFix(2, TTYPE_BITS)
val X_WRITE_UNCACHED = UFix(3, TTYPE_BITS)
val X_INIT_TYPE_BITS = 2
val X_INIT_READ_SHARED = UFix(0, X_INIT_TYPE_BITS)
val X_INIT_READ_EXCLUSIVE = UFix(1, X_INIT_TYPE_BITS)
val X_INIT_READ_UNCACHED = UFix(2, X_INIT_TYPE_BITS)
val X_INIT_WRITE_UNCACHED = UFix(3, X_INIT_TYPE_BITS)
val PTYPE_BITS = 2
val P_INVALIDATE = UFix(0, PTYPE_BITS)
val P_DOWNGRADE = UFix(1, PTYPE_BITS)
val P_COPY = UFix(2, PTYPE_BITS)
val X_REP_TYPE_BITS = 3
val X_REP_READ_SHARED = UFix(0, X_REP_TYPE_BITS)
val X_REP_READ_EXCLUSIVE = UFix(1, X_REP_TYPE_BITS)
val X_REP_READ_UNCACHED = UFix(2, X_REP_TYPE_BITS)
val X_REP_WRITE_UNCACHED = UFix(3, X_REP_TYPE_BITS)
val X_REP_READ_EXCLUSIVE_ACK = UFix(4, X_REP_TYPE_BITS)
val P_REQ_TYPE_BITS = 2
val P_REQ_INVALIDATE = UFix(0, P_REQ_TYPE_BITS)
val P_REQ_DOWNGRADE = UFix(1, P_REQ_TYPE_BITS)
val P_REQ_COPY = UFix(2, P_REQ_TYPE_BITS)
val P_REP_TYPE_BITS = 3
val P_REP_INVALIDATE_DATA = UFix(0, P_REP_TYPE_BITS)
val P_REP_DOWNGRADE_DATA = UFix(1, P_REP_TYPE_BITS)
val P_REP_COPY_DATA = UFix(2, P_REP_TYPE_BITS)
val P_REP_INVALIDATE_ACK = UFix(3, P_REP_TYPE_BITS)
val P_REP_DOWNGRADE_ACK = UFix(4, P_REP_TYPE_BITS)
val P_REP_COPY_ACK = UFix(5, P_REP_TYPE_BITS)
// external memory interface
val MEM_TAG_BITS = 4