From 1b3307df32f48e2fc1cc83c6bbc8f8170dbf95b9 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 2 Mar 2012 23:51:53 -0800 Subject: [PATCH] Removed has_data fields from all coherence messages, increased message type names to compensate --- rocket/src/main/scala/coherence.scala | 78 ++++++++++++--------- rocket/src/main/scala/consts.scala | 33 ++++++--- rocket/src/main/scala/htif.scala | 3 +- rocket/src/main/scala/icache.scala | 3 +- rocket/src/main/scala/icache_prefetch.scala | 3 +- rocket/src/main/scala/nbdcache.scala | 8 +-- 6 files changed, 73 insertions(+), 55 deletions(-) diff --git a/rocket/src/main/scala/coherence.scala b/rocket/src/main/scala/coherence.scala index 4532794b..0ce1f1c9 100644 --- a/rocket/src/main/scala/coherence.scala +++ b/rocket/src/main/scala/coherence.scala @@ -42,8 +42,7 @@ class TrackerAllocReq extends Bundle { class TransactionInit extends Bundle { - val t_type = Bits(width = TTYPE_BITS) - val has_data = Bool() + val t_type = Bits(width = X_INIT_TYPE_BITS) val tile_xact_id = Bits(width = TILE_XACT_ID_BITS) val address = UFix(width = PADDR_BITS) } @@ -55,21 +54,20 @@ class TransactionAbort extends Bundle { } class ProbeRequest extends Bundle { - val p_type = Bits(width = PTYPE_BITS) + val p_type = Bits(width = P_REQ_TYPE_BITS) val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS) val address = Bits(width = PADDR_BITS) } class ProbeReply extends Bundle { - val p_type = Bits(width = PTYPE_BITS) - val has_data = Bool() + val p_type = Bits(width = P_REP_TYPE_BITS) val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS) } class ProbeReplyData extends MemData class TransactionReply extends MemData { - val t_type = Bits(width = TTYPE_BITS) + val t_type = Bits(width = X_REP_TYPE_BITS) val tile_xact_id = Bits(width = TILE_XACT_ID_BITS) val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS) } @@ -162,17 +160,17 @@ trait FourStateCoherence extends CoherencePolicy { } def newStateOnTransactionRep(incoming: TransactionReply, outstanding: TransactionInit): UFix = { MuxLookup(incoming.t_type, tileInvalid, Array( - X_READ_SHARED -> tileShared, - X_READ_EXCLUSIVE -> Mux(outstanding.t_type === X_READ_EXCLUSIVE, tileExclusiveDirty, tileExclusiveClean), - X_READ_EXCLUSIVE_ACK -> tileExclusiveDirty, - X_READ_UNCACHED -> tileInvalid, - X_WRITE_UNCACHED -> tileInvalid + X_REP_READ_SHARED -> tileShared, + X_REP_READ_EXCLUSIVE -> Mux(outstanding.t_type === X_INIT_READ_EXCLUSIVE, tileExclusiveDirty, tileExclusiveClean), + X_REP_READ_EXCLUSIVE_ACK -> tileExclusiveDirty, + X_REP_READ_UNCACHED -> tileInvalid, + X_REP_WRITE_UNCACHED -> tileInvalid )) } def needsSecondaryXact(cmd: Bits, outstanding: TransactionInit): Bool = { val (read, write) = cpuCmdToRW(cmd) - (read && (outstanding.t_type === X_READ_UNCACHED || outstanding.t_type === X_WRITE_UNCACHED)) || - (write && (outstanding.t_type != X_READ_EXCLUSIVE)) + (read && (outstanding.t_type === X_INIT_READ_UNCACHED || outstanding.t_type === X_INIT_WRITE_UNCACHED)) || + (write && (outstanding.t_type != X_INIT_READ_EXCLUSIVE)) } def newStateOnProbeReq(incoming: ProbeRequest, state: UFix): Bits = { @@ -183,12 +181,20 @@ trait FourStateCoherence extends CoherencePolicy { )) } - def replyTypeHasData (reply: TransactionReply): Bool = { - (reply.t_type != X_WRITE_UNCACHED && reply.t_type != X_READ_EXCLUSIVE_ACK) + def probeReplyHasData (reply: ProbeReply): Bool = { + (reply.p_type === P_REP_INVALIDATE_DATA || + reply.p_type === P_REP_DOWNGRADE_DATA || + reply.p_type === P_REP_COPY_DATA) + } + def transactionInitHasData (init: TransactionInit): Bool = { + (init.t_type != X_INIT_WRITE_UNCACHED) + } + def transactionReplyHasData (reply: TransactionReply): Bool = { + (reply.t_type != X_REP_WRITE_UNCACHED && reply.t_type != X_REP_READ_EXCLUSIVE_ACK) } } -class XactTracker(id: Int) extends Component with CoherencePolicy { +class XactTracker(id: Int) extends Component with FourStateCoherence { val io = new Bundle { val alloc_req = (new ioDecoupled) { new TrackerAllocReq }.flip val p_data = (new ioPipe) { new TrackerProbeData } @@ -210,7 +216,7 @@ class XactTracker(id: Int) extends Component with CoherencePolicy { val p_rep_tile_id = Bits(TILE_ID_BITS, OUTPUT) val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT) val sharer_count = Bits(TILE_ID_BITS+1, OUTPUT) - val t_type = Bits(TTYPE_BITS, OUTPUT) + val t_type = Bits(X_INIT_TYPE_BITS, OUTPUT) val push_p_req = Bits(NTILES, OUTPUT) val pop_p_rep = Bits(NTILES, OUTPUT) val pop_p_rep_data = Bits(NTILES, OUTPUT) @@ -220,18 +226,20 @@ class XactTracker(id: Int) extends Component with CoherencePolicy { } def sendProbeReqType(t_type: UFix, global_state: UFix): UFix = { - MuxCase(P_COPY, Array((t_type === X_READ_SHARED) -> P_DOWNGRADE, - (t_type === X_READ_EXCLUSIVE) -> P_INVALIDATE, - (t_type === X_READ_UNCACHED) -> P_COPY, - (t_type === X_WRITE_UNCACHED) -> P_INVALIDATE)) + MuxLookup(t_type, P_REQ_COPY, Array( + X_INIT_READ_SHARED -> P_REQ_DOWNGRADE, + X_INIT_READ_EXCLUSIVE -> P_REQ_INVALIDATE, + X_INIT_READ_UNCACHED -> P_REQ_COPY, + X_INIT_WRITE_UNCACHED -> P_REQ_INVALIDATE + )) } def needsMemRead(t_type: UFix, global_state: UFix): Bool = { - (t_type != X_WRITE_UNCACHED) + (t_type != X_INIT_WRITE_UNCACHED) } def needsAckRep(t_type: UFix, global_state: UFix): Bool = { - (t_type === X_WRITE_UNCACHED) + (t_type === X_INIT_WRITE_UNCACHED) } val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() } @@ -312,7 +320,7 @@ class XactTracker(id: Int) extends Component with CoherencePolicy { t_type_ := io.alloc_req.bits.xact_init.t_type init_tile_id_ := io.alloc_req.bits.init_tile_id tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id - x_init_data_needs_write := io.alloc_req.bits.xact_init.has_data + x_init_data_needs_write := transactionInitHasData(io.alloc_req.bits.xact_init) x_needs_read := needsMemRead(io.alloc_req.bits.xact_init.t_type, UFix(0)) p_rep_count := UFix(NTILES-1) p_req_flags := ~( UFix(1) << io.alloc_req.bits.init_tile_id ) @@ -378,7 +386,7 @@ abstract class CoherenceHub extends Component with CoherencePolicy { class CoherenceHubNull extends CoherenceHub { val x_init = io.tiles(0).xact_init - val is_write = x_init.bits.t_type === X_WRITE_UNCACHED + val is_write = x_init.bits.t_type === X_INIT_WRITE_UNCACHED x_init.ready := io.mem.req_cmd.ready && !(is_write && io.mem.resp.valid) //stall write req/resp to handle previous read resp io.mem.req_cmd.valid := x_init.valid && !(is_write && io.mem.resp.valid) io.mem.req_cmd.bits.rw := is_write @@ -387,7 +395,7 @@ class CoherenceHubNull extends CoherenceHub { io.mem.req_data <> io.tiles(0).xact_init_data val x_rep = io.tiles(0).xact_rep - x_rep.bits.t_type := Mux(io.mem.resp.valid, X_READ_EXCLUSIVE, X_WRITE_UNCACHED) + x_rep.bits.t_type := Mux(io.mem.resp.valid, X_REP_READ_EXCLUSIVE, X_REP_WRITE_UNCACHED) x_rep.bits.tile_xact_id := Mux(io.mem.resp.valid, io.mem.resp.bits.tag, x_init.bits.tile_xact_id) x_rep.bits.global_xact_id := UFix(0) // don't care x_rep.bits.data := io.mem.resp.bits.data @@ -395,17 +403,17 @@ class CoherenceHubNull extends CoherenceHub { } -class CoherenceHubBroadcast extends CoherenceHub { +class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{ def coherenceConflict(addr1: Bits, addr2: Bits): Bool = { addr1(PADDR_BITS-1, OFFSET_BITS) === addr2(PADDR_BITS-1, OFFSET_BITS) } def getTransactionReplyType(t_type: UFix, count: UFix): Bits = { - MuxLookup(t_type, X_READ_UNCACHED, Array( - X_READ_SHARED -> Mux(count > UFix(0), X_READ_SHARED, X_READ_EXCLUSIVE), - X_READ_EXCLUSIVE -> X_READ_EXCLUSIVE, - X_READ_UNCACHED -> X_READ_UNCACHED, - X_WRITE_UNCACHED -> X_WRITE_UNCACHED + MuxLookup(t_type, X_REP_READ_UNCACHED, Array( + X_INIT_READ_SHARED -> Mux(count > UFix(0), X_REP_READ_SHARED, X_REP_READ_EXCLUSIVE), + X_INIT_READ_EXCLUSIVE -> X_REP_READ_EXCLUSIVE, + X_INIT_READ_UNCACHED -> X_REP_READ_UNCACHED, + X_INIT_WRITE_UNCACHED -> X_REP_WRITE_UNCACHED )) } @@ -415,7 +423,7 @@ class CoherenceHubBroadcast extends CoherenceHub { val addr_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS)} } val init_tile_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} } val tile_xact_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} } - val t_type_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TTYPE_BITS)} } + val t_type_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=X_INIT_TYPE_BITS)} } val sh_count_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} } val send_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} } @@ -506,7 +514,7 @@ class CoherenceHubBroadcast extends CoherenceHub { val idx = p_rep.bits.global_xact_id p_rep.ready := foldR(trackerList.map(_.io.pop_p_rep(j)))(_ || _) p_rep_data.ready := foldR(trackerList.map(_.io.pop_p_rep_data(j)))(_ || _) - p_data_valid_arr(idx) := p_rep.valid && p_rep.bits.has_data + p_data_valid_arr(idx) := p_rep.valid && probeReplyHasData(p_rep.bits) p_data_tile_id_arr(idx) := UFix(j) } for( i <- 0 until NGLOBAL_XACTS ) { @@ -527,7 +535,7 @@ class CoherenceHubBroadcast extends CoherenceHub { for( i <- 0 until NGLOBAL_XACTS) { val t = trackerList(i).io conflicts(UFix(i), t.busy && coherenceConflict(t.addr, x_init.bits.address) && - !(x_init.bits.has_data && (UFix(j) === t.init_tile_id))) + !(transactionInitHasData(x_init.bits) && (UFix(j) === t.init_tile_id))) // Don't abort writebacks stalled on mem. // TODO: This assumes overlapped writeback init reqs to // the same addr will never be issued; is this ok? diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index f0c2432a..4159e952 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -191,16 +191,31 @@ object Constants val GLOBAL_XACT_ID_BITS = 4 val NGLOBAL_XACTS = 1 << GLOBAL_XACT_ID_BITS - val TTYPE_BITS = 2 - val X_READ_SHARED = UFix(0, TTYPE_BITS) - val X_READ_EXCLUSIVE = UFix(1, TTYPE_BITS) - val X_READ_UNCACHED = UFix(2, TTYPE_BITS) - val X_WRITE_UNCACHED = UFix(3, TTYPE_BITS) + val X_INIT_TYPE_BITS = 2 + val X_INIT_READ_SHARED = UFix(0, X_INIT_TYPE_BITS) + val X_INIT_READ_EXCLUSIVE = UFix(1, X_INIT_TYPE_BITS) + val X_INIT_READ_UNCACHED = UFix(2, X_INIT_TYPE_BITS) + val X_INIT_WRITE_UNCACHED = UFix(3, X_INIT_TYPE_BITS) - val PTYPE_BITS = 2 - val P_INVALIDATE = UFix(0, PTYPE_BITS) - val P_DOWNGRADE = UFix(1, PTYPE_BITS) - val P_COPY = UFix(2, PTYPE_BITS) + val X_REP_TYPE_BITS = 3 + val X_REP_READ_SHARED = UFix(0, X_REP_TYPE_BITS) + val X_REP_READ_EXCLUSIVE = UFix(1, X_REP_TYPE_BITS) + val X_REP_READ_UNCACHED = UFix(2, X_REP_TYPE_BITS) + val X_REP_WRITE_UNCACHED = UFix(3, X_REP_TYPE_BITS) + val X_REP_READ_EXCLUSIVE_ACK = UFix(4, X_REP_TYPE_BITS) + + val P_REQ_TYPE_BITS = 2 + val P_REQ_INVALIDATE = UFix(0, P_REQ_TYPE_BITS) + val P_REQ_DOWNGRADE = UFix(1, P_REQ_TYPE_BITS) + val P_REQ_COPY = UFix(2, P_REQ_TYPE_BITS) + + val P_REP_TYPE_BITS = 3 + val P_REP_INVALIDATE_DATA = UFix(0, P_REP_TYPE_BITS) + val P_REP_DOWNGRADE_DATA = UFix(1, P_REP_TYPE_BITS) + val P_REP_COPY_DATA = UFix(2, P_REP_TYPE_BITS) + val P_REP_INVALIDATE_ACK = UFix(3, P_REP_TYPE_BITS) + val P_REP_DOWNGRADE_ACK = UFix(4, P_REP_TYPE_BITS) + val P_REP_COPY_ACK = UFix(5, P_REP_TYPE_BITS) // external memory interface val MEM_TAG_BITS = 4 diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index 0357d359..6dedbc16 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -117,8 +117,7 @@ class rocketHTIF(w: Int, ncores: Int) extends Component mem_req_data = Cat(packet_ram.read(idx), mem_req_data) } io.mem.xact_init.valid := state === state_mem_req - io.mem.xact_init.bits.t_type := Mux(cmd === cmd_writemem, X_WRITE_UNCACHED, X_READ_UNCACHED) - io.mem.xact_init.bits.has_data := cmd === cmd_writemem + io.mem.xact_init.bits.t_type := Mux(cmd === cmd_writemem, X_INIT_WRITE_UNCACHED, X_INIT_READ_UNCACHED) io.mem.xact_init.bits.address := addr >> UFix(OFFSET_BITS-3) io.mem.xact_init_data.valid:= state === state_mem_wdata diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 3d18f974..6ca20c3e 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -129,8 +129,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component { rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit); io.cpu.resp_data := data_mux.io.out io.mem.xact_init.valid := (state === s_request) - io.mem.xact_init.bits.t_type := X_READ_UNCACHED - io.mem.xact_init.bits.has_data := Bool(false) + io.mem.xact_init.bits.t_type := X_INIT_READ_UNCACHED io.mem.xact_init.bits.address := r_cpu_miss_addr(tagmsb,indexlsb).toUFix io.mem.xact_init_data.valid := Bool(false) diff --git a/rocket/src/main/scala/icache_prefetch.scala b/rocket/src/main/scala/icache_prefetch.scala index ba666cd9..9ad85d82 100644 --- a/rocket/src/main/scala/icache_prefetch.scala +++ b/rocket/src/main/scala/icache_prefetch.scala @@ -30,8 +30,7 @@ class rocketIPrefetcher extends Component() { val ip_mem_resp_val = io.mem.xact_rep.valid && io.mem.xact_rep.bits.tile_xact_id(0) io.mem.xact_init.valid := prefetch_miss || (state === s_req_wait) - io.mem.xact_init.bits.t_type := X_READ_UNCACHED - io.mem.xact_init.bits.has_data := Bool(false) + io.mem.xact_init.bits.t_type := X_INIT_READ_UNCACHED io.mem.xact_init.bits.tile_xact_id := Mux(prefetch_miss, UFix(0), UFix(1)) io.mem.xact_init.bits.address := Mux(prefetch_miss, io.icache.xact_init.bits.address, prefetch_addr); io.mem.xact_init_data.valid := Bool(false) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index b99701c6..a5dc640b 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -240,8 +240,7 @@ class MSHR(id: Int) extends Component with ThreeStateIncoherence { io.meta_req.bits.way_en := way_oh_ io.mem_req.valid := valid && !requested - io.mem_req.bits.t_type := Mux(needsWriteback(next_state), X_READ_EXCLUSIVE, X_READ_SHARED) - io.mem_req.bits.has_data := Bool(false) + io.mem_req.bits.t_type := Mux(needsWriteback(next_state), X_INIT_READ_EXCLUSIVE, X_INIT_READ_SHARED) io.mem_req.bits.address := Cat(ppn, idx_).toUFix io.mem_req.bits.tile_xact_id := Bits(id) @@ -380,8 +379,7 @@ class WritebackUnit extends Component { val wb_req_val = io.req.valid && !valid io.refill_req.ready := io.mem_req.ready && !wb_req_val io.mem_req.valid := io.refill_req.valid || wb_req_val - io.mem_req.bits.t_type := Mux(wb_req_val, X_WRITE_UNCACHED, io.refill_req.bits.t_type) - io.mem_req.bits.has_data := wb_req_val + io.mem_req.bits.t_type := Mux(wb_req_val, X_INIT_WRITE_UNCACHED, io.refill_req.bits.t_type) io.mem_req.bits.address := Mux(wb_req_val, Cat(io.req.bits.ppn, io.req.bits.idx).toUFix, io.refill_req.bits.address) io.mem_req.bits.tile_xact_id := Mux(wb_req_val, Bits(NMSHR), io.refill_req.bits.tile_xact_id) @@ -679,7 +677,7 @@ class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence { // refill counter val mem_resp_type = io.mem.xact_rep.bits.t_type - val refill_val = io.mem.xact_rep.valid && (mem_resp_type === X_READ_SHARED || mem_resp_type === X_READ_EXCLUSIVE) + val refill_val = io.mem.xact_rep.valid && (mem_resp_type === X_REP_READ_SHARED || mem_resp_type === X_REP_READ_EXCLUSIVE) val rr_count = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES))) val rr_count_next = rr_count + UFix(1) when (refill_val) { rr_count := rr_count_next }