riscv/rocket-chip
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TileLinkIO.GrantAck -> TileLinkIO.Finish

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This commit is contained in:
Henry Cook 2014-04-26 15:18:21 -07:00
parent fc825c7103
commit 1b156c6db9
3 changed files with 8 additions and 8 deletions
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4
rocket/src/main/scala/icache.scala
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@ -271,7 +271,7 @@ class ICache(implicit c: ICacheConfig) extends Module
io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word) io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word)
io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout) io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
val ack_q = Module(new Queue(new LogicalNetworkIO(new GrantAck), 1)) val ack_q = Module(new Queue(new LogicalNetworkIO(new Finish), 1))
ack_q.io.enq.valid := refill_done && tl.co.requiresAckForGrant(refill_bits.payload.g_type) ack_q.io.enq.valid := refill_done && tl.co.requiresAckForGrant(refill_bits.payload.g_type)
ack_q.io.enq.bits.payload.master_xact_id := refill_bits.payload.master_xact_id ack_q.io.enq.bits.payload.master_xact_id := refill_bits.payload.master_xact_id
ack_q.io.enq.bits.header.dst := refill_bits.header.src ack_q.io.enq.bits.header.dst := refill_bits.header.src
@ -280,7 +280,7 @@ class ICache(implicit c: ICacheConfig) extends Module
io.resp.valid := s2_hit io.resp.valid := s2_hit
io.mem.acquire.valid := (state === s_request) && ack_q.io.enq.ready io.mem.acquire.valid := (state === s_request) && ack_q.io.enq.ready
io.mem.acquire.bits.payload := Acquire(tl.co.getUncachedReadAcquireType, s2_addr >> UInt(c.offbits), UInt(0)) io.mem.acquire.bits.payload := Acquire(tl.co.getUncachedReadAcquireType, s2_addr >> UInt(c.offbits), UInt(0))
io.mem.grant_ack <> ack_q.io.deq io.mem.finish <> ack_q.io.deq
// control state machine // control state machine
switch (state) { switch (state) {

10
rocket/src/main/scala/nbdcache.scala
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@ -142,7 +142,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
val meta_write = Decoupled(new MetaWriteReq) val meta_write = Decoupled(new MetaWriteReq)
val replay = Decoupled(new Replay) val replay = Decoupled(new Replay)
val mem_grant = Valid(new LogicalNetworkIO(new Grant)).flip val mem_grant = Valid(new LogicalNetworkIO(new Grant)).flip
val mem_finish = Decoupled(new LogicalNetworkIO(new GrantAck)) val mem_finish = Decoupled(new LogicalNetworkIO(new Finish))
val wb_req = Decoupled(new WritebackReq) val wb_req = Decoupled(new WritebackReq)
val probe_rdy = Bool(OUTPUT) val probe_rdy = Bool(OUTPUT)
} }
@ -224,7 +224,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
} }
} }
val ackq = Module(new Queue(new LogicalNetworkIO(new GrantAck), 1)) val ackq = Module(new Queue(new LogicalNetworkIO(new Finish), 1))
ackq.io.enq.valid := (wb_done || refill_done) && tl.co.requiresAckForGrant(io.mem_grant.bits.payload.g_type) ackq.io.enq.valid := (wb_done || refill_done) && tl.co.requiresAckForGrant(io.mem_grant.bits.payload.g_type)
ackq.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id ackq.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id
ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src
@ -292,7 +292,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Module {
val meta_write = Decoupled(new MetaWriteReq) val meta_write = Decoupled(new MetaWriteReq)
val replay = Decoupled(new Replay) val replay = Decoupled(new Replay)
val mem_grant = Valid(new LogicalNetworkIO(new Grant)).flip val mem_grant = Valid(new LogicalNetworkIO(new Grant)).flip
val mem_finish = Decoupled(new LogicalNetworkIO(new GrantAck)) val mem_finish = Decoupled(new LogicalNetworkIO(new Finish))
val wb_req = Decoupled(new WritebackReq) val wb_req = Decoupled(new WritebackReq)
val probe_rdy = Bool(OUTPUT) val probe_rdy = Bool(OUTPUT)
@ -315,7 +315,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Module {
val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, conf.nmshr)) val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, conf.nmshr))
val meta_write_arb = Module(new Arbiter(new MetaWriteReq, conf.nmshr)) val meta_write_arb = Module(new Arbiter(new MetaWriteReq, conf.nmshr))
val mem_req_arb = Module(new Arbiter(new Acquire, conf.nmshr)) val mem_req_arb = Module(new Arbiter(new Acquire, conf.nmshr))
val mem_finish_arb = Module(new Arbiter(new LogicalNetworkIO(new GrantAck), conf.nmshr)) val mem_finish_arb = Module(new Arbiter(new LogicalNetworkIO(new Finish), conf.nmshr))
val wb_req_arb = Module(new Arbiter(new WritebackReq, conf.nmshr)) val wb_req_arb = Module(new Arbiter(new WritebackReq, conf.nmshr))
val replay_arb = Module(new Arbiter(new Replay, conf.nmshr)) val replay_arb = Module(new Arbiter(new Replay, conf.nmshr))
val alloc_arb = Module(new Arbiter(Bool(), conf.nmshr)) val alloc_arb = Module(new Arbiter(Bool(), conf.nmshr))
@ -992,7 +992,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
io.cpu.replay_next.valid := s1_replay && (s1_read || s1_sc) io.cpu.replay_next.valid := s1_replay && (s1_read || s1_sc)
io.cpu.replay_next.bits := s1_req.tag io.cpu.replay_next.bits := s1_req.tag
io.mem.grant_ack <> mshrs.io.mem_finish io.mem.finish <> mshrs.io.mem_finish
} }
// exposes a sane decoupled request interface // exposes a sane decoupled request interface

2
rocket/src/main/scala/tile.scala
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@ -75,7 +75,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module
io.tilelink.acquire <> memArb.io.out.acquire io.tilelink.acquire <> memArb.io.out.acquire
memArb.io.out.grant <> io.tilelink.grant memArb.io.out.grant <> io.tilelink.grant
io.tilelink.grant_ack <> memArb.io.out.grant_ack io.tilelink.finish <> memArb.io.out.finish
dcache.io.mem.probe <> io.tilelink.probe dcache.io.mem.probe <> io.tilelink.probe
io.tilelink.release.valid := dcache.io.mem.release.valid io.tilelink.release.valid := dcache.io.mem.release.valid
dcache.io.mem.release.ready := io.tilelink.release.ready dcache.io.mem.release.ready := io.tilelink.release.ready