From 1b156c6db941bd1d6885983b0e0b459c66ba58b3 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Sat, 26 Apr 2014 15:18:21 -0700 Subject: [PATCH] TileLinkIO.GrantAck -> TileLinkIO.Finish --- rocket/src/main/scala/icache.scala | 4 ++-- rocket/src/main/scala/nbdcache.scala | 10 +++++----- rocket/src/main/scala/tile.scala | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 742905b7..9bc4c617 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -271,7 +271,7 @@ class ICache(implicit c: ICacheConfig) extends Module io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word) io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout) - val ack_q = Module(new Queue(new LogicalNetworkIO(new GrantAck), 1)) + val ack_q = Module(new Queue(new LogicalNetworkIO(new Finish), 1)) ack_q.io.enq.valid := refill_done && tl.co.requiresAckForGrant(refill_bits.payload.g_type) ack_q.io.enq.bits.payload.master_xact_id := refill_bits.payload.master_xact_id ack_q.io.enq.bits.header.dst := refill_bits.header.src @@ -280,7 +280,7 @@ class ICache(implicit c: ICacheConfig) extends Module io.resp.valid := s2_hit io.mem.acquire.valid := (state === s_request) && ack_q.io.enq.ready io.mem.acquire.bits.payload := Acquire(tl.co.getUncachedReadAcquireType, s2_addr >> UInt(c.offbits), UInt(0)) - io.mem.grant_ack <> ack_q.io.deq + io.mem.finish <> ack_q.io.deq // control state machine switch (state) { diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index f639e392..ac2bce26 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -142,7 +142,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module { val meta_write = Decoupled(new MetaWriteReq) val replay = Decoupled(new Replay) val mem_grant = Valid(new LogicalNetworkIO(new Grant)).flip - val mem_finish = Decoupled(new LogicalNetworkIO(new GrantAck)) + val mem_finish = Decoupled(new LogicalNetworkIO(new Finish)) val wb_req = Decoupled(new WritebackReq) val probe_rdy = Bool(OUTPUT) } @@ -224,7 +224,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module { } } - val ackq = Module(new Queue(new LogicalNetworkIO(new GrantAck), 1)) + val ackq = Module(new Queue(new LogicalNetworkIO(new Finish), 1)) ackq.io.enq.valid := (wb_done || refill_done) && tl.co.requiresAckForGrant(io.mem_grant.bits.payload.g_type) ackq.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src @@ -292,7 +292,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Module { val meta_write = Decoupled(new MetaWriteReq) val replay = Decoupled(new Replay) val mem_grant = Valid(new LogicalNetworkIO(new Grant)).flip - val mem_finish = Decoupled(new LogicalNetworkIO(new GrantAck)) + val mem_finish = Decoupled(new LogicalNetworkIO(new Finish)) val wb_req = Decoupled(new WritebackReq) val probe_rdy = Bool(OUTPUT) @@ -315,7 +315,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Module { val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, conf.nmshr)) val meta_write_arb = Module(new Arbiter(new MetaWriteReq, conf.nmshr)) val mem_req_arb = Module(new Arbiter(new Acquire, conf.nmshr)) - val mem_finish_arb = Module(new Arbiter(new LogicalNetworkIO(new GrantAck), conf.nmshr)) + val mem_finish_arb = Module(new Arbiter(new LogicalNetworkIO(new Finish), conf.nmshr)) val wb_req_arb = Module(new Arbiter(new WritebackReq, conf.nmshr)) val replay_arb = Module(new Arbiter(new Replay, conf.nmshr)) val alloc_arb = Module(new Arbiter(Bool(), conf.nmshr)) @@ -992,7 +992,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module { io.cpu.replay_next.valid := s1_replay && (s1_read || s1_sc) io.cpu.replay_next.bits := s1_req.tag - io.mem.grant_ack <> mshrs.io.mem_finish + io.mem.finish <> mshrs.io.mem_finish } // exposes a sane decoupled request interface diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 56cdbef4..94beb86d 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -75,7 +75,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module io.tilelink.acquire <> memArb.io.out.acquire memArb.io.out.grant <> io.tilelink.grant - io.tilelink.grant_ack <> memArb.io.out.grant_ack + io.tilelink.finish <> memArb.io.out.finish dcache.io.mem.probe <> io.tilelink.probe io.tilelink.release.valid := dcache.io.mem.release.valid dcache.io.mem.release.ready := io.tilelink.release.ready