riscv/rocket-chip
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remove icache req_rdy signal

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This commit is contained in:
Andrew Waterman 2012-01-11 18:27:11 -08:00
parent bcb55e581a
commit 1a7bfd4350
3 changed files with 5 additions and 9 deletions
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1
rocket/src/main/scala/cpu.scala
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@ -60,7 +60,6 @@ class rocketProc extends Component
io.imem.req_ppn := itlb.io.cpu.resp_ppn; io.imem.req_ppn := itlb.io.cpu.resp_ppn;
io.imem.req_val := ctrl.io.imem.req_val; io.imem.req_val := ctrl.io.imem.req_val;
io.imem.invalidate := ctrl.io.flush_inst; io.imem.invalidate := ctrl.io.flush_inst;
ctrl.io.imem.req_rdy := itlb.io.cpu.req_rdy && io.imem.req_rdy;
ctrl.io.imem.resp_val := io.imem.resp_val; ctrl.io.imem.resp_val := io.imem.resp_val;
dpath.io.imem.resp_data := io.imem.resp_data; dpath.io.imem.resp_data := io.imem.resp_data;
ctrl.io.xcpt_itlb := itlb.io.cpu.exception; ctrl.io.xcpt_itlb := itlb.io.cpu.exception;

3
rocket/src/main/scala/ctrl.scala
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@ -75,7 +75,7 @@ class ioCtrlAll extends Bundle()
{ {
val dpath = new ioCtrlDpath(); val dpath = new ioCtrlDpath();
val console = new ioConsole(List("rdy")); val console = new ioConsole(List("rdy"));
val imem = new ioImem(List("req_val", "req_rdy", "resp_val")).flip(); val imem = new ioImem(List("req_val", "resp_val")).flip();
val dmem = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_replay", "resp_nack")).flip(); val dmem = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_replay", "resp_nack")).flip();
val dtlb_val = Bool('output); val dtlb_val = Bool('output);
val dtlb_kill = Bool('output); val dtlb_kill = Bool('output);
@ -586,7 +586,6 @@ class rocketCtrl extends Component
io.dpath.stallf := io.dpath.stallf :=
~take_pc & ~take_pc &
( (
~io.imem.req_rdy |
~io.imem.resp_val | ~io.imem.resp_val |
io.dpath.stalld io.dpath.stalld
); );

10
rocket/src/main/scala/icache.scala
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@ -54,12 +54,13 @@ class rocketICacheDM(lines: Int) extends Component {
val offsetlsb = ceil(log(databits/8)/log(2)).toInt; val offsetlsb = ceil(log(databits/8)/log(2)).toInt;
val rf_cnt_bits = ceil(log(REFILL_CYCLES)/log(2)).toInt; val rf_cnt_bits = ceil(log(REFILL_CYCLES)/log(2)).toInt;
val s_reset :: s_ready :: s_request :: s_refill_wait :: s_refill :: s_resolve_miss :: Nil = Enum(6) { UFix() }; val s_reset :: s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(5) { UFix() };
val state = Reg(resetVal = s_reset); val state = Reg(resetVal = s_reset);
val r_cpu_req_idx = Reg { Bits(width = PGIDX_BITS) } val r_cpu_req_idx = Reg { Bits(width = PGIDX_BITS) }
val r_cpu_req_ppn = Reg { Bits(width = PPN_BITS) } val r_cpu_req_ppn = Reg { Bits(width = PPN_BITS) }
val r_cpu_req_val = Reg(resetVal = Bool(false)); val r_cpu_req_val = Reg(resetVal = Bool(false));
val r_rdy = Reg(io.cpu.req_rdy)
when (io.cpu.req_val && io.cpu.req_rdy) { when (io.cpu.req_val && io.cpu.req_rdy) {
r_cpu_req_idx <== io.cpu.req_idx; r_cpu_req_idx <== io.cpu.req_idx;
@ -111,7 +112,7 @@ class rocketICacheDM(lines: Int) extends Component {
val data_array_rdata = data_array.rw(data_addr, io.mem.resp_data, io.mem.resp_val); val data_array_rdata = data_array.rw(data_addr, io.mem.resp_data, io.mem.resp_val);
// output signals // output signals
io.cpu.resp_val := !io.cpu.itlb_miss && (state === s_ready) && r_cpu_req_val && tag_valid && tag_match; io.cpu.resp_val := !io.cpu.itlb_miss && (state === s_ready) && r_rdy && r_cpu_req_val && tag_valid && tag_match;
io.cpu.req_rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || (tag_valid && tag_match)); io.cpu.req_rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || (tag_valid && tag_match));
io.cpu.resp_data := data_array_rdata >> Cat(r_cpu_req_idx(offsetmsb-rf_cnt_bits,offsetlsb), UFix(0, log2up(databits))).toUFix io.cpu.resp_data := data_array_rdata >> Cat(r_cpu_req_idx(offsetmsb-rf_cnt_bits,offsetlsb), UFix(0, log2up(databits))).toUFix
io.mem.req_val := (state === s_request); io.mem.req_val := (state === s_request);
@ -143,12 +144,9 @@ class rocketICacheDM(lines: Int) extends Component {
} }
is (s_refill) { is (s_refill) {
when (io.mem.resp_val && (~refill_count === UFix(0))) { when (io.mem.resp_val && (~refill_count === UFix(0))) {
state <== s_resolve_miss; state <== s_ready;
} }
} }
is (s_resolve_miss) {
state <== s_ready;
}
} }
} }