From 1a7bfd4350c0ea2aa944a30f3bd5871a69179fae Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@s143.Millennium.Berkeley.EDU>
Date: Wed, 11 Jan 2012 18:27:11 -0800
Subject: [PATCH] remove icache req_rdy signal

---
 rocket/src/main/scala/cpu.scala    |  1 -
 rocket/src/main/scala/ctrl.scala   |  3 +--
 rocket/src/main/scala/icache.scala | 10 ++++------
 3 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala
index 5497f727..fc7e0494 100644
--- a/rocket/src/main/scala/cpu.scala
+++ b/rocket/src/main/scala/cpu.scala
@@ -60,7 +60,6 @@ class rocketProc extends Component
   io.imem.req_ppn         := itlb.io.cpu.resp_ppn;
   io.imem.req_val         := ctrl.io.imem.req_val;
   io.imem.invalidate      := ctrl.io.flush_inst;
-  ctrl.io.imem.req_rdy    := itlb.io.cpu.req_rdy && io.imem.req_rdy;  
   ctrl.io.imem.resp_val   := io.imem.resp_val;
   dpath.io.imem.resp_data := io.imem.resp_data;
   ctrl.io.xcpt_itlb       := itlb.io.cpu.exception;
diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index 6db925fe..1333c65e 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -75,7 +75,7 @@ class ioCtrlAll extends Bundle()
 {
   val dpath   = new ioCtrlDpath();
   val console = new ioConsole(List("rdy"));
-  val imem    = new ioImem(List("req_val", "req_rdy", "resp_val")).flip();
+  val imem    = new ioImem(List("req_val", "resp_val")).flip();
   val dmem    = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_replay", "resp_nack")).flip();
   val dtlb_val = Bool('output);
   val dtlb_kill = Bool('output);
@@ -586,7 +586,6 @@ class rocketCtrl extends Component
   io.dpath.stallf :=
     ~take_pc &
     (
-      ~io.imem.req_rdy |
       ~io.imem.resp_val |
       io.dpath.stalld
     );
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 870a3ee2..462cbd4c 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -54,12 +54,13 @@ class rocketICacheDM(lines: Int) extends Component {
   val offsetlsb = ceil(log(databits/8)/log(2)).toInt;
   val rf_cnt_bits = ceil(log(REFILL_CYCLES)/log(2)).toInt;
   
-  val s_reset :: s_ready :: s_request :: s_refill_wait :: s_refill :: s_resolve_miss :: Nil = Enum(6) { UFix() };
+  val s_reset :: s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(5) { UFix() };
   val state = Reg(resetVal = s_reset);
   
   val r_cpu_req_idx    = Reg { Bits(width = PGIDX_BITS) }
   val r_cpu_req_ppn    = Reg { Bits(width = PPN_BITS) }
   val r_cpu_req_val    = Reg(resetVal = Bool(false));
+  val r_rdy = Reg(io.cpu.req_rdy)
   
   when (io.cpu.req_val && io.cpu.req_rdy) {
     r_cpu_req_idx   <== io.cpu.req_idx;
@@ -111,7 +112,7 @@ class rocketICacheDM(lines: Int) extends Component {
   val data_array_rdata = data_array.rw(data_addr, io.mem.resp_data, io.mem.resp_val);
 
   // output signals
-  io.cpu.resp_val := !io.cpu.itlb_miss && (state === s_ready) && r_cpu_req_val && tag_valid && tag_match; 
+  io.cpu.resp_val := !io.cpu.itlb_miss && (state === s_ready) && r_rdy && r_cpu_req_val && tag_valid && tag_match; 
   io.cpu.req_rdy  := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || (tag_valid && tag_match));
   io.cpu.resp_data := data_array_rdata >> Cat(r_cpu_req_idx(offsetmsb-rf_cnt_bits,offsetlsb), UFix(0, log2up(databits))).toUFix
   io.mem.req_val := (state === s_request);
@@ -143,12 +144,9 @@ class rocketICacheDM(lines: Int) extends Component {
     }
     is (s_refill) {
       when (io.mem.resp_val && (~refill_count === UFix(0))) {
-        state <== s_resolve_miss;
+        state <== s_ready;
       }
     }
-    is (s_resolve_miss) {
-      state <== s_ready;
-    }
   }  
 }