riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

Merge branch 'master' into priv-1.10

Browse Source
This commit is contained in:
Henry Cook authored and GitHub committed 2017-03-13 11:59:18 -07:00
2 parents dbc8f4b30b 1c6dde8c15
commit 1a3fec61c0
2 files changed
+2 -2
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

src/main/scala/uncore/tilelink2/ToAHB.scala
+1 -1
View File
@@ -30,7 +30,7 @@ case class TLToAHBNode() extends MixedAdapterNode(TLImp, AHBImp)(
TLManagerPortParameters(managers, beatBytes, 1, 1)
})
class TLToAHB(combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
class TLToAHB(val combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
{
val node = TLToAHBNode()
src/main/scala/uncore/tilelink2/ToAXI4.scala
+1 -1
View File
@@ -35,7 +35,7 @@ case class TLToAXI4Node(idBits: Int) extends MixedAdapterNode(TLImp, AXI4Imp)(
minLatency = p.minLatency)
})
class TLToAXI4(idBits: Int, combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
class TLToAXI4(val idBits: Int, val combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
{
val node = TLToAXI4Node(idBits)