From 75512e9aa09ee8696bf31806f8109d43d4ec2f8d Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Thu, 1 Dec 2016 14:55:25 -0800 Subject: [PATCH 01/12] minor Changes needed to support formal tests --- src/main/scala/diplomacy/LazyModule.scala | 3 +++ src/main/scala/uncore/tilelink2/Edges.scala | 18 ++++++++++++++++++ .../scala/uncore/tilelink2/Fragmenter.scala | 2 +- src/main/scala/uncore/tilelink2/Monitor.scala | 4 ++++ .../scala/uncore/tilelink2/Parameters.scala | 4 ++-- 5 files changed, 28 insertions(+), 3 deletions(-) diff --git a/src/main/scala/diplomacy/LazyModule.scala b/src/main/scala/diplomacy/LazyModule.scala index 5de4877c..79bf3b6d 100644 --- a/src/main/scala/diplomacy/LazyModule.scala +++ b/src/main/scala/diplomacy/LazyModule.scala @@ -91,7 +91,10 @@ object LazyModule protected[diplomacy] var stack = List[LazyModule]() private var index = 0 + var module_list = List[LazyModule]() + def apply[T <: LazyModule](bc: T)(implicit sourceInfo: SourceInfo): T = { + module_list = bc :: module_list // Make sure the user put LazyModule around modules in the correct order // If this require fails, probably some grandchild was missing a LazyModule // ... or you applied LazyModule twice diff --git a/src/main/scala/uncore/tilelink2/Edges.scala b/src/main/scala/uncore/tilelink2/Edges.scala index a7cb2df6..4df9a1b5 100644 --- a/src/main/scala/uncore/tilelink2/Edges.scala +++ b/src/main/scala/uncore/tilelink2/Edges.scala @@ -95,6 +95,24 @@ class TLEdge( staticHasData(x).map(Bool(_)).getOrElse(opdata) } + def opcode(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.opcode + case b: TLBundleB => b.opcode + case c: TLBundleC => c.opcode + case d: TLBundleD => d.opcode + } + } + + def param(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.param + case b: TLBundleB => b.param + case c: TLBundleC => c.param + case d: TLBundleD => d.param + } + } + def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala index 3c5c319f..4e6592dc 100644 --- a/src/main/scala/uncore/tilelink2/Fragmenter.scala +++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala @@ -13,7 +13,7 @@ import scala.math.{min,max} // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides -class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) extends LazyModule +class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false) extends LazyModule { require (isPow2 (maxSize)) require (isPow2 (minSize)) diff --git a/src/main/scala/uncore/tilelink2/Monitor.scala b/src/main/scala/uncore/tilelink2/Monitor.scala index a8af77e3..b993c490 100644 --- a/src/main/scala/uncore/tilelink2/Monitor.scala +++ b/src/main/scala/uncore/tilelink2/Monitor.scala @@ -415,11 +415,15 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source legalizeSourceUnique(bundle, edge) } + var code_insertion = (bundle_monitor: TLBundleSnoop, edge: TLEdge) => {} + lazy val module = new LazyModuleImp(this) { val io = new Bundle { val in = gen().asInput } + code_insertion(io.in, edge()) + legalize(io.in, edge())(sourceInfo) } } diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index f732efd9..19dd9604 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -7,9 +7,9 @@ import diplomacy._ import scala.math.max case class TLManagerParameters( - address: Seq[AddressSet], + val address: Seq[AddressSet], regionType: RegionType.T = RegionType.GET_EFFECTS, - executable: Boolean = false, // processor can execute from this memory + val executable: Boolean = false, // processor can execute from this memory nodePath: Seq[BaseNode] = Seq(), // Supports both Acquire+Release+Finish of these sizes supportsAcquire: TransferSizes = TransferSizes.none, From 5e9496fd14b0ca648aea69ac933023476c61bc27 Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Thu, 1 Dec 2016 14:55:25 -0800 Subject: [PATCH 02/12] minor Changes needed to support formal tests --- src/main/scala/diplomacy/LazyModule.scala | 3 +++ src/main/scala/uncore/tilelink2/Edges.scala | 18 ++++++++++++++++++ .../scala/uncore/tilelink2/Fragmenter.scala | 2 +- src/main/scala/uncore/tilelink2/Monitor.scala | 4 ++++ .../scala/uncore/tilelink2/Parameters.scala | 4 ++-- 5 files changed, 28 insertions(+), 3 deletions(-) diff --git a/src/main/scala/diplomacy/LazyModule.scala b/src/main/scala/diplomacy/LazyModule.scala index 3b7de281..52824f47 100644 --- a/src/main/scala/diplomacy/LazyModule.scala +++ b/src/main/scala/diplomacy/LazyModule.scala @@ -91,7 +91,10 @@ object LazyModule protected[diplomacy] var stack = List[LazyModule]() private var index = 0 + var module_list = List[LazyModule]() + def apply[T <: LazyModule](bc: T)(implicit sourceInfo: SourceInfo): T = { + module_list = bc :: module_list // Make sure the user put LazyModule around modules in the correct order // If this require fails, probably some grandchild was missing a LazyModule // ... or you applied LazyModule twice diff --git a/src/main/scala/uncore/tilelink2/Edges.scala b/src/main/scala/uncore/tilelink2/Edges.scala index 92deb987..e794d846 100644 --- a/src/main/scala/uncore/tilelink2/Edges.scala +++ b/src/main/scala/uncore/tilelink2/Edges.scala @@ -95,6 +95,24 @@ class TLEdge( staticHasData(x).map(Bool(_)).getOrElse(opdata) } + def opcode(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.opcode + case b: TLBundleB => b.opcode + case c: TLBundleC => c.opcode + case d: TLBundleD => d.opcode + } + } + + def param(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.param + case b: TLBundleB => b.param + case c: TLBundleC => c.param + case d: TLBundleD => d.param + } + } + def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala index fd9a44d2..21817bb1 100644 --- a/src/main/scala/uncore/tilelink2/Fragmenter.scala +++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala @@ -13,7 +13,7 @@ import scala.math.{min,max} // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides -class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) extends LazyModule +class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false) extends LazyModule { require (isPow2 (maxSize)) require (isPow2 (minSize)) diff --git a/src/main/scala/uncore/tilelink2/Monitor.scala b/src/main/scala/uncore/tilelink2/Monitor.scala index 9af850fd..072ecb11 100644 --- a/src/main/scala/uncore/tilelink2/Monitor.scala +++ b/src/main/scala/uncore/tilelink2/Monitor.scala @@ -415,11 +415,15 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source legalizeSourceUnique(bundle, edge) } + var code_insertion = (bundle_monitor: TLBundleSnoop, edge: TLEdge) => {} + lazy val module = new LazyModuleImp(this) { val io = new Bundle { val in = gen().asInput } + code_insertion(io.in, edge()) + legalize(io.in, edge())(sourceInfo) } } diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index 7418d575..b60dea6d 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -7,9 +7,9 @@ import diplomacy._ import scala.math.max case class TLManagerParameters( - address: Seq[AddressSet], + val address: Seq[AddressSet], regionType: RegionType.T = RegionType.GET_EFFECTS, - executable: Boolean = false, // processor can execute from this memory + val executable: Boolean = false, // processor can execute from this memory nodePath: Seq[BaseNode] = Seq(), // Supports both Acquire+Release+Finish of these sizes supportsAcquire: TransferSizes = TransferSizes.none, From cff2612cdb2ac0eb9e353cd28b748795a3479007 Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Thu, 1 Dec 2016 14:55:25 -0800 Subject: [PATCH 03/12] minor Changes needed to support formal tests --- src/main/scala/diplomacy/LazyModule.scala | 3 +++ src/main/scala/uncore/tilelink2/Edges.scala | 18 ++++++++++++++++++ .../scala/uncore/tilelink2/Fragmenter.scala | 2 +- src/main/scala/uncore/tilelink2/Monitor.scala | 4 ++++ .../scala/uncore/tilelink2/Parameters.scala | 4 ++-- 5 files changed, 28 insertions(+), 3 deletions(-) diff --git a/src/main/scala/diplomacy/LazyModule.scala b/src/main/scala/diplomacy/LazyModule.scala index 3b7de281..52824f47 100644 --- a/src/main/scala/diplomacy/LazyModule.scala +++ b/src/main/scala/diplomacy/LazyModule.scala @@ -91,7 +91,10 @@ object LazyModule protected[diplomacy] var stack = List[LazyModule]() private var index = 0 + var module_list = List[LazyModule]() + def apply[T <: LazyModule](bc: T)(implicit sourceInfo: SourceInfo): T = { + module_list = bc :: module_list // Make sure the user put LazyModule around modules in the correct order // If this require fails, probably some grandchild was missing a LazyModule // ... or you applied LazyModule twice diff --git a/src/main/scala/uncore/tilelink2/Edges.scala b/src/main/scala/uncore/tilelink2/Edges.scala index 92deb987..e794d846 100644 --- a/src/main/scala/uncore/tilelink2/Edges.scala +++ b/src/main/scala/uncore/tilelink2/Edges.scala @@ -95,6 +95,24 @@ class TLEdge( staticHasData(x).map(Bool(_)).getOrElse(opdata) } + def opcode(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.opcode + case b: TLBundleB => b.opcode + case c: TLBundleC => c.opcode + case d: TLBundleD => d.opcode + } + } + + def param(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.param + case b: TLBundleB => b.param + case c: TLBundleC => c.param + case d: TLBundleD => d.param + } + } + def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala index fd9a44d2..21817bb1 100644 --- a/src/main/scala/uncore/tilelink2/Fragmenter.scala +++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala @@ -13,7 +13,7 @@ import scala.math.{min,max} // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides -class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) extends LazyModule +class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false) extends LazyModule { require (isPow2 (maxSize)) require (isPow2 (minSize)) diff --git a/src/main/scala/uncore/tilelink2/Monitor.scala b/src/main/scala/uncore/tilelink2/Monitor.scala index 9af850fd..072ecb11 100644 --- a/src/main/scala/uncore/tilelink2/Monitor.scala +++ b/src/main/scala/uncore/tilelink2/Monitor.scala @@ -415,11 +415,15 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source legalizeSourceUnique(bundle, edge) } + var code_insertion = (bundle_monitor: TLBundleSnoop, edge: TLEdge) => {} + lazy val module = new LazyModuleImp(this) { val io = new Bundle { val in = gen().asInput } + code_insertion(io.in, edge()) + legalize(io.in, edge())(sourceInfo) } } diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index 7418d575..b60dea6d 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -7,9 +7,9 @@ import diplomacy._ import scala.math.max case class TLManagerParameters( - address: Seq[AddressSet], + val address: Seq[AddressSet], regionType: RegionType.T = RegionType.GET_EFFECTS, - executable: Boolean = false, // processor can execute from this memory + val executable: Boolean = false, // processor can execute from this memory nodePath: Seq[BaseNode] = Seq(), // Supports both Acquire+Release+Finish of these sizes supportsAcquire: TransferSizes = TransferSizes.none, From 6d402ff1afb4fcf940806162d41f55bab9ea7b23 Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Thu, 1 Dec 2016 14:55:25 -0800 Subject: [PATCH 04/12] minor Changes needed to support formal tests --- src/main/scala/diplomacy/LazyModule.scala | 3 +++ src/main/scala/uncore/tilelink2/Edges.scala | 18 ++++++++++++++++++ .../scala/uncore/tilelink2/Fragmenter.scala | 2 +- src/main/scala/uncore/tilelink2/Monitor.scala | 4 ++++ .../scala/uncore/tilelink2/Parameters.scala | 4 ++-- 5 files changed, 28 insertions(+), 3 deletions(-) diff --git a/src/main/scala/diplomacy/LazyModule.scala b/src/main/scala/diplomacy/LazyModule.scala index 3b7de281..52824f47 100644 --- a/src/main/scala/diplomacy/LazyModule.scala +++ b/src/main/scala/diplomacy/LazyModule.scala @@ -91,7 +91,10 @@ object LazyModule protected[diplomacy] var stack = List[LazyModule]() private var index = 0 + var module_list = List[LazyModule]() + def apply[T <: LazyModule](bc: T)(implicit sourceInfo: SourceInfo): T = { + module_list = bc :: module_list // Make sure the user put LazyModule around modules in the correct order // If this require fails, probably some grandchild was missing a LazyModule // ... or you applied LazyModule twice diff --git a/src/main/scala/uncore/tilelink2/Edges.scala b/src/main/scala/uncore/tilelink2/Edges.scala index 92deb987..e794d846 100644 --- a/src/main/scala/uncore/tilelink2/Edges.scala +++ b/src/main/scala/uncore/tilelink2/Edges.scala @@ -95,6 +95,24 @@ class TLEdge( staticHasData(x).map(Bool(_)).getOrElse(opdata) } + def opcode(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.opcode + case b: TLBundleB => b.opcode + case c: TLBundleC => c.opcode + case d: TLBundleD => d.opcode + } + } + + def param(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.param + case b: TLBundleB => b.param + case c: TLBundleC => c.param + case d: TLBundleD => d.param + } + } + def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala index fd9a44d2..21817bb1 100644 --- a/src/main/scala/uncore/tilelink2/Fragmenter.scala +++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala @@ -13,7 +13,7 @@ import scala.math.{min,max} // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides -class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) extends LazyModule +class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false) extends LazyModule { require (isPow2 (maxSize)) require (isPow2 (minSize)) diff --git a/src/main/scala/uncore/tilelink2/Monitor.scala b/src/main/scala/uncore/tilelink2/Monitor.scala index 9af850fd..072ecb11 100644 --- a/src/main/scala/uncore/tilelink2/Monitor.scala +++ b/src/main/scala/uncore/tilelink2/Monitor.scala @@ -415,11 +415,15 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source legalizeSourceUnique(bundle, edge) } + var code_insertion = (bundle_monitor: TLBundleSnoop, edge: TLEdge) => {} + lazy val module = new LazyModuleImp(this) { val io = new Bundle { val in = gen().asInput } + code_insertion(io.in, edge()) + legalize(io.in, edge())(sourceInfo) } } diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index 7418d575..b60dea6d 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -7,9 +7,9 @@ import diplomacy._ import scala.math.max case class TLManagerParameters( - address: Seq[AddressSet], + val address: Seq[AddressSet], regionType: RegionType.T = RegionType.GET_EFFECTS, - executable: Boolean = false, // processor can execute from this memory + val executable: Boolean = false, // processor can execute from this memory nodePath: Seq[BaseNode] = Seq(), // Supports both Acquire+Release+Finish of these sizes supportsAcquire: TransferSizes = TransferSizes.none, From be23189f77a4c482066dedbbb0520a1b66953263 Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Thu, 1 Dec 2016 18:35:43 -0800 Subject: [PATCH 05/12] Removed val from case class for Parameters --- src/main/scala/uncore/tilelink2/Parameters.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index b60dea6d..7418d575 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -7,9 +7,9 @@ import diplomacy._ import scala.math.max case class TLManagerParameters( - val address: Seq[AddressSet], + address: Seq[AddressSet], regionType: RegionType.T = RegionType.GET_EFFECTS, - val executable: Boolean = false, // processor can execute from this memory + executable: Boolean = false, // processor can execute from this memory nodePath: Seq[BaseNode] = Seq(), // Supports both Acquire+Release+Finish of these sizes supportsAcquire: TransferSizes = TransferSizes.none, From 053f81d7c6078a4efeb7ba8d9916c6f98cc4428d Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Thu, 1 Dec 2016 14:55:25 -0800 Subject: [PATCH 06/12] minor Changes needed to support formal tests --- src/main/scala/diplomacy/LazyModule.scala | 3 +++ src/main/scala/uncore/tilelink2/Edges.scala | 18 ++++++++++++++++++ .../scala/uncore/tilelink2/Fragmenter.scala | 2 +- src/main/scala/uncore/tilelink2/Monitor.scala | 4 ++++ .../scala/uncore/tilelink2/Parameters.scala | 4 ++-- 5 files changed, 28 insertions(+), 3 deletions(-) diff --git a/src/main/scala/diplomacy/LazyModule.scala b/src/main/scala/diplomacy/LazyModule.scala index 3b7de281..52824f47 100644 --- a/src/main/scala/diplomacy/LazyModule.scala +++ b/src/main/scala/diplomacy/LazyModule.scala @@ -91,7 +91,10 @@ object LazyModule protected[diplomacy] var stack = List[LazyModule]() private var index = 0 + var module_list = List[LazyModule]() + def apply[T <: LazyModule](bc: T)(implicit sourceInfo: SourceInfo): T = { + module_list = bc :: module_list // Make sure the user put LazyModule around modules in the correct order // If this require fails, probably some grandchild was missing a LazyModule // ... or you applied LazyModule twice diff --git a/src/main/scala/uncore/tilelink2/Edges.scala b/src/main/scala/uncore/tilelink2/Edges.scala index 92deb987..e794d846 100644 --- a/src/main/scala/uncore/tilelink2/Edges.scala +++ b/src/main/scala/uncore/tilelink2/Edges.scala @@ -95,6 +95,24 @@ class TLEdge( staticHasData(x).map(Bool(_)).getOrElse(opdata) } + def opcode(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.opcode + case b: TLBundleB => b.opcode + case c: TLBundleC => c.opcode + case d: TLBundleD => d.opcode + } + } + + def param(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.param + case b: TLBundleB => b.param + case c: TLBundleC => c.param + case d: TLBundleD => d.param + } + } + def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala index fd9a44d2..21817bb1 100644 --- a/src/main/scala/uncore/tilelink2/Fragmenter.scala +++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala @@ -13,7 +13,7 @@ import scala.math.{min,max} // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides -class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) extends LazyModule +class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false) extends LazyModule { require (isPow2 (maxSize)) require (isPow2 (minSize)) diff --git a/src/main/scala/uncore/tilelink2/Monitor.scala b/src/main/scala/uncore/tilelink2/Monitor.scala index 9af850fd..072ecb11 100644 --- a/src/main/scala/uncore/tilelink2/Monitor.scala +++ b/src/main/scala/uncore/tilelink2/Monitor.scala @@ -415,11 +415,15 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source legalizeSourceUnique(bundle, edge) } + var code_insertion = (bundle_monitor: TLBundleSnoop, edge: TLEdge) => {} + lazy val module = new LazyModuleImp(this) { val io = new Bundle { val in = gen().asInput } + code_insertion(io.in, edge()) + legalize(io.in, edge())(sourceInfo) } } diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index 7418d575..b60dea6d 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -7,9 +7,9 @@ import diplomacy._ import scala.math.max case class TLManagerParameters( - address: Seq[AddressSet], + val address: Seq[AddressSet], regionType: RegionType.T = RegionType.GET_EFFECTS, - executable: Boolean = false, // processor can execute from this memory + val executable: Boolean = false, // processor can execute from this memory nodePath: Seq[BaseNode] = Seq(), // Supports both Acquire+Release+Finish of these sizes supportsAcquire: TransferSizes = TransferSizes.none, From e8d3b647f29a522e017eda5108671be5a1fe21ff Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Thu, 1 Dec 2016 18:35:43 -0800 Subject: [PATCH 07/12] Removed val from case class for Parameters --- src/main/scala/uncore/tilelink2/Parameters.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index b60dea6d..7418d575 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -7,9 +7,9 @@ import diplomacy._ import scala.math.max case class TLManagerParameters( - val address: Seq[AddressSet], + address: Seq[AddressSet], regionType: RegionType.T = RegionType.GET_EFFECTS, - val executable: Boolean = false, // processor can execute from this memory + executable: Boolean = false, // processor can execute from this memory nodePath: Seq[BaseNode] = Seq(), // Supports both Acquire+Release+Finish of these sizes supportsAcquire: TransferSizes = TransferSizes.none, From 54cc071a64bddaec065dbee7fae9b1a69bc8bf8c Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Wed, 7 Dec 2016 16:22:05 -0800 Subject: [PATCH 08/12] Fix Fragmenter to ensure logical operations must be sent out atomically. Edited Fuzzer so that it can generate infinite operations when nOperations is net to 0 --- .../scala/uncore/tilelink2/Fragmenter.scala | 2 +- src/main/scala/uncore/tilelink2/Fuzzer.scala | 28 +++++++++++++------ 2 files changed, 20 insertions(+), 10 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala index 21817bb1..1c95c78e 100644 --- a/src/main/scala/uncore/tilelink2/Fragmenter.scala +++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala @@ -31,7 +31,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = TransferSizes.none def mapManager(m: TLManagerParameters) = m.copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), - supportsLogical = expandTransfer(m.supportsLogical), + supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet), supportsPutFull = expandTransfer(m.supportsPutFull), supportsPutPartial = expandTransfer(m.supportsPutPartial), diff --git a/src/main/scala/uncore/tilelink2/Fuzzer.scala b/src/main/scala/uncore/tilelink2/Fuzzer.scala index 38756238..9122545f 100644 --- a/src/main/scala/uncore/tilelink2/Fuzzer.scala +++ b/src/main/scala/uncore/tilelink2/Fuzzer.scala @@ -108,9 +108,13 @@ class TLFuzzer( val dataBits = edge.bundle.dataBits // Progress through operations - val num_reqs = Reg(init = UInt(nOperations-1, log2Up(nOperations))) - val num_resps = Reg(init = UInt(nOperations-1, log2Up(nOperations))) - io.finished := num_resps === UInt(0) + val num_reqs = Reg(init = UInt(nOperations, log2Up(nOperations))) + val num_resps = Reg(init = UInt(nOperations, log2Up(nOperations))) + if (nOperations>0) { + io.finished := num_resps === UInt(0) + } else { + io.finished := Bool(false) + } // Progress within each operation val a = out.a.bits @@ -179,7 +183,11 @@ class TLFuzzer( UInt("b101") -> hbits)) // Wire both the used and un-used channel signals - out.a.valid := legal && alloc.valid && num_reqs =/= UInt(0) + if (nOperations>0) { + out.a.valid := legal && alloc.valid && num_reqs =/= UInt(0) + } else { + out.a.valid := legal && alloc.valid + } out.a.bits := bits out.b.ready := Bool(true) out.c.valid := Bool(false) @@ -190,12 +198,14 @@ class TLFuzzer( inc := !legal || req_done inc_beat := !legal || out.a.fire() - when (out.a.fire() && a_last) { - num_reqs := num_reqs - UInt(1) - } + if (nOperations>0) { + when (out.a.fire() && a_last) { + num_reqs := num_reqs - UInt(1) + } - when (out.d.fire() && d_last) { - num_resps := num_resps - UInt(1) + when (out.d.fire() && d_last) { + num_resps := num_resps - UInt(1) + } } } } From 4c3083c18137daa160a78a53b516323d7c9ea3af Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Fri, 9 Dec 2016 16:44:30 -0800 Subject: [PATCH 09/12] Remove unnecessary val --- src/main/scala/uncore/tilelink2/Parameters.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index b60dea6d..7418d575 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -7,9 +7,9 @@ import diplomacy._ import scala.math.max case class TLManagerParameters( - val address: Seq[AddressSet], + address: Seq[AddressSet], regionType: RegionType.T = RegionType.GET_EFFECTS, - val executable: Boolean = false, // processor can execute from this memory + executable: Boolean = false, // processor can execute from this memory nodePath: Seq[BaseNode] = Seq(), // Supports both Acquire+Release+Finish of these sizes supportsAcquire: TransferSizes = TransferSizes.none, From aae9b2303684bbcef1b577d350c10696137034b8 Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Mon, 12 Dec 2016 16:16:56 -0800 Subject: [PATCH 10/12] Update with paratermized LazyModule --- src/main/scala/uncore/tilelink2/Monitor.scala | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/Monitor.scala b/src/main/scala/uncore/tilelink2/Monitor.scala index 1e3a57c3..184fe9a0 100644 --- a/src/main/scala/uncore/tilelink2/Monitor.scala +++ b/src/main/scala/uncore/tilelink2/Monitor.scala @@ -13,18 +13,14 @@ abstract class TLMonitorBase(args: TLMonitorArgs) extends LazyModule()(args.p) { implicit val sourceInfo = args.sourceInfo - def legalize(bundle: TLBundleSnoop, edge: TLEdge): Unit + def legalize(bundle: TLBundleSnoop, edge: TLEdge, reset: Bool): Unit - var code_insertion = (bundle_monitor: TLBundleSnoop, edge: TLEdge) => {} - lazy val module = new LazyModuleImp(this) { val io = new Bundle { val in = args.gen().asInput } - code_insertion(io.in, edge()) - - legalize(io.in, args.edge()) + legalize(io.in, args.edge(), reset) } } @@ -431,7 +427,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args) inflight := (inflight | a_set) & ~d_clr } - def legalize(bundle: TLBundleSnoop, edge: TLEdge) { + def legalize(bundle: TLBundleSnoop, edge: TLEdge, reset: Bool) { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeSourceUnique(bundle, edge) From ec425a1d143c54f78b86f43baed815c655b5d110 Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Mon, 12 Dec 2016 16:18:37 -0800 Subject: [PATCH 11/12] Merge with Head --- torture | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/torture b/torture index b95d8ea3..77195ab1 160000 --- a/torture +++ b/torture @@ -1 +1 @@ -Subproject commit b95d8ea3b2273d2a95e421de0d78ab1b280c96b0 +Subproject commit 77195ab12aefc373ca688e0a9c4d710c13191341 From 531f3684ed2f7de36d916656ea3e72fd4f58e3d9 Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Mon, 12 Dec 2016 16:25:31 -0800 Subject: [PATCH 12/12] Removing module list for merging. (will need to create iterator in future) --- src/main/scala/diplomacy/LazyModule.scala | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/main/scala/diplomacy/LazyModule.scala b/src/main/scala/diplomacy/LazyModule.scala index 7aabd9ea..d97bbf7f 100644 --- a/src/main/scala/diplomacy/LazyModule.scala +++ b/src/main/scala/diplomacy/LazyModule.scala @@ -92,10 +92,7 @@ object LazyModule protected[diplomacy] var stack = List[LazyModule]() private var index = 0 - var module_list = List[LazyModule]() - def apply[T <: LazyModule](bc: T)(implicit sourceInfo: SourceInfo): T = { - module_list = bc :: module_list // Make sure the user put LazyModule around modules in the correct order // If this require fails, probably some grandchild was missing a LazyModule // ... or you applied LazyModule twice