riscv/rocket-chip
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Only set id_reg_fence when AMO/FENCE is actually executed

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This is a performance bug, not a correctness bug.  But randomly stalling
because of garbage bits coming out of the I$ should be avoided.

h/t @solomatnikov
This commit is contained in:
Andrew Waterman 2017-04-03 16:26:57 -07:00 committed by Andrew Waterman
parent 629e9a2ef6
commit 19f0ae64a0
1 changed files with 2 additions and 1 deletions
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3
src/main/scala/rocket/Rocket.scala
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@ -213,10 +213,10 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
val id_amo_rl = id_inst(0)(25)
val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_rl
val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid
when (!id_mem_busy) { id_reg_fence := false }
val id_rocc_busy = Bool(usingRoCC) &&
(io.rocc.busy || ex_reg_valid && ex_ctrl.rocc ||
mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc)
id_reg_fence := id_fence_next || id_reg_fence && id_mem_busy
val id_do_fence = id_rocc_busy && id_ctrl.fence ||
id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc))
@ -294,6 +294,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
ex_ctrl := id_ctrl
ex_reg_rvc := ibuf.io.inst(0).bits.rvc
ex_ctrl.csr := id_csr
when (id_fence_next) { id_reg_fence := true }
when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr
ex_ctrl.alu_fn := ALU.FN_ADD
ex_ctrl.alu_dw := DW_XPR