From 19f0ae64a0d978f7ee107f46c49c4a7e8339c115 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 3 Apr 2017 16:26:57 -0700 Subject: [PATCH] Only set id_reg_fence when AMO/FENCE is actually executed This is a performance bug, not a correctness bug. But randomly stalling because of garbage bits coming out of the I$ should be avoided. h/t @solomatnikov --- src/main/scala/rocket/Rocket.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/rocket/Rocket.scala b/src/main/scala/rocket/Rocket.scala index 22552498..98e527d8 100644 --- a/src/main/scala/rocket/Rocket.scala +++ b/src/main/scala/rocket/Rocket.scala @@ -213,10 +213,10 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) val id_amo_rl = id_inst(0)(25) val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_rl val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid + when (!id_mem_busy) { id_reg_fence := false } val id_rocc_busy = Bool(usingRoCC) && (io.rocc.busy || ex_reg_valid && ex_ctrl.rocc || mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc) - id_reg_fence := id_fence_next || id_reg_fence && id_mem_busy val id_do_fence = id_rocc_busy && id_ctrl.fence || id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc)) @@ -294,6 +294,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) ex_ctrl := id_ctrl ex_reg_rvc := ibuf.io.inst(0).bits.rvc ex_ctrl.csr := id_csr + when (id_fence_next) { id_reg_fence := true } when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr ex_ctrl.alu_fn := ALU.FN_ADD ex_ctrl.alu_dw := DW_XPR