riscv/rocket-chip
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use default constructors for IOMSHR acquire construction

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This commit is contained in:
Howard Mao 2015-11-12 11:40:40 -08:00
parent 59ca373146
commit 19daee10f0
1 changed files with 20 additions and 13 deletions
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33
rocket/src/main/scala/nbdcache.scala
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@ -169,26 +169,33 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val beat_mask = (storegen.mask << Cat(beat_offset, UInt(0, wordOffBits))) val beat_mask = (storegen.mask << Cat(beat_offset, UInt(0, wordOffBits)))
val beat_data = Fill(beatWords, storegen.data) val beat_data = Fill(beatWords, storegen.data)
val addr_byte = req.addr(beatOffBits - 1, 0)
val a_type = Mux(isRead(req.cmd), Acquire.getType, Acquire.putType)
val union = Mux(isRead(req.cmd),
Cat(addr_byte, req.typ, M_XRD), beat_mask)
val s_idle :: s_acquire :: s_grant :: s_resp :: Nil = Enum(Bits(), 4) val s_idle :: s_acquire :: s_grant :: s_resp :: Nil = Enum(Bits(), 4)
val state = Reg(init = s_idle) val state = Reg(init = s_idle)
io.req.ready := (state === s_idle) io.req.ready := (state === s_idle)
io.acquire.valid := (state === s_acquire) val addr_block = req.addr(paddrBits - 1, blockOffBits)
io.acquire.bits := Acquire( val addr_beat = req.addr(blockOffBits - 1, beatOffBits)
is_builtin_type = Bool(true), val addr_byte = req.addr(beatOffBits - 1, 0)
a_type = a_type,
val get_acquire = Get(
client_xact_id = UInt(id), client_xact_id = UInt(id),
addr_block = req.addr(paddrBits - 1, blockOffBits), addr_block = addr_block,
addr_beat = req.addr(blockOffBits - 1, beatOffBits), addr_beat = addr_beat,
addr_byte = addr_byte,
operand_size = req.typ,
alloc = Bool(false))
val put_acquire = Put(
client_xact_id = UInt(id),
addr_block = addr_block,
addr_beat = addr_beat,
data = beat_data, data = beat_data,
// alloc bit should always be false wmask = beat_mask,
union = Cat(union, Bool(false))) alloc = Bool(false))
io.acquire.valid := (state === s_acquire)
io.acquire.bits := Mux(isRead(req.cmd), get_acquire, put_acquire)
io.resp.valid := (state === s_resp) io.resp.valid := (state === s_resp)
io.resp.bits := req io.resp.bits := req