riscv/rocket-chip
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a few more fixes. some param lookups fail (here() in Alter blocks)

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This commit is contained in:
Henry Cook 2014-08-10 23:08:21 -07:00
parent 63bd0b9d2a
commit 1983260e6f
2 changed files with 8 additions and 7 deletions
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2
rocket

@ -1 +1 @@
Subproject commit 6beea1debbdd8115f45d02318210df624e67e9f8 Subproject commit f0f84ed6f953388a046c3296ccd0a3640ca6bd48

13
src/main/scala/RocketChip.scala
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@ -109,10 +109,10 @@ class DefaultConfig extends ChiselConfig {
case Entries => 62 case Entries => 62
case NRAS => 2 case NRAS => 2
case MatchBits => site(PgIdxBits) case MatchBits => site(PgIdxBits)
case Pages => ((1 max(log2Up(here(Entries))))+1)/2*2 case Pages => ((1 max(log2Up(site(Entries))))+1)/2*2 //TODO PARAMS no here?
// control logic assumes 2 divides pages // control logic assumes 2 divides pages
case OpaqueBits => log2Up(here(Entries)) case OpaqueBits => log2Up(here(Entries))
case NBHT => 1 << log2Up(here(Entries)*2) case NBHT => 1 << log2Up(site(Entries)*2) //TODO PARAMS no here?
}) })
//MemoryConstants //MemoryConstants
case "CACHE_DATA_SIZE_IN_BYTES" => 1 << 6 case "CACHE_DATA_SIZE_IN_BYTES" => 1 << 6
@ -132,9 +132,9 @@ class DefaultConfig extends ChiselConfig {
case TileLinkL1Params => Alter({ case TileLinkL1Params => Alter({
case LNMasters => site[Int]("NBANKS") case LNMasters => site[Int]("NBANKS")
case LNClients => site[Int]("NTILES")+1 case LNClients => site[Int]("NTILES")+1
case LNEndpoints => here(LNMasters) + here(LNClients) case LNEndpoints => site[Int]("NBANKS") + site[Int]("NTILES")+1 // TODO PARAMS why broken?: site(LNMasters) +site(LNClients)
case TLCoherence => site(Coherence) case TLCoherence => site(Coherence)
case TLAddrBits => site[Int]("PADDR_BITS") - site[Int]("OFFSET_BITS") case TLAddrBits => site(PAddrBits) - site[Int]("OFFSET_BITS")
case TLMasterXactIdBits => log2Up(site[Int]("NL2_REL_XACTS")+site[Int]("NL2_ACQ_XACTS")) case TLMasterXactIdBits => log2Up(site[Int]("NL2_REL_XACTS")+site[Int]("NL2_ACQ_XACTS"))
case TLClientXactIdBits => 2*log2Up(site[Int]("NMSHRS")*site[Int]("NTILES")+1) case TLClientXactIdBits => 2*log2Up(site[Int]("NMSHRS")*site[Int]("NTILES")+1)
case TLDataBits => site[Int]("CACHE_DATA_SIZE_IN_BYTES")*8 case TLDataBits => site[Int]("CACHE_DATA_SIZE_IN_BYTES")*8
@ -348,9 +348,10 @@ class Top extends Module {
val nTiles = params(NTiles) val nTiles = params(NTiles)
val io = new VLSITopIO val io = new VLSITopIO
params.alter(params(TileLinkL1Params)) val tl: PartialFunction[Any,Any] = params(TileLinkL1Params) //TODO PARAMS can't lookup in map() below?
params.alter(tl)
val resetSigs = Vec.fill(nTiles){Bool()} val resetSigs = Vec.fill(nTiles){Bool()}
val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r)))) val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r)), tl))//TODO PARAMS above alter() is insufficient?
val uncore = Module(new Uncore) val uncore = Module(new Uncore)
for (i <- 0 until nTiles) { for (i <- 0 until nTiles) {